Sync push

CMakeLists.txt

@@ -34,6 +34,7 @@ list(APPEND RUNTIME_SOURCE_FILES
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/CPU.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/RAM.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/BUS.cpp
+	${CMAKE_CURRENT_LIST_DIR}/src/hardware/MMU.cpp
 )
 list(APPEND DEBUGGER_SOURCE_FILES
 	${CMAKE_CURRENT_LIST_DIR}/src/debugger/debugger_main.cpp
@@ -41,6 +42,7 @@ list(APPEND DEBUGGER_SOURCE_FILES
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/CPU.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/RAM.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/BUS.cpp
+	${CMAKE_CURRENT_LIST_DIR}/src/hardware/MMU.cpp
 )
 list(APPEND ASSEMBLER_SOURCE_FILES
 	${CMAKE_CURRENT_LIST_DIR}/src/assembler/assembler_main.cpp
@@ -52,6 +54,7 @@ list(APPEND TEST_SOURCE_FILES
 	${CMAKE_CURRENT_LIST_DIR}/src/RAM_test.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/RAM.cpp
 	${CMAKE_CURRENT_LIST_DIR}/src/hardware/BUS.cpp
+	${CMAKE_CURRENT_LIST_DIR}/src/hardware/MMU.cpp
 )
 #-----------------------------------------------------------------------------------------
 

other/build.nr

@@ -1 +1 @@
-12
+13

src/common/Data.hpp

@@ -31,6 +31,13 @@ namespace dragon
 	using PhysicalAddress = AddressType;
 	// --------------------------------
 
+	enum class RegAccess {
+		UserReadWrite,           // FL (if you split out I)
+		UserReadOnly,            // CORE_ID, CYCLE
+		SupervisorReadWrite,     // IV, EPC, CAUSE, PTB, ASID, etc.
+		SupervisorReadOnly       // (none currently, but reserved)
+	};
+
 	enum class MMUAccessType : u8 { Read, Write, Execute };
 	enum class MMUAccessMode : u8 { Privileged, User };
 	enum class MMUFaultKind : u8 { PageFault, PrivPageFault, Bounds, Misalignment };

src/hardware/CPU.cpp

@@ -24,23 +24,24 @@ namespace dragon
 {
 	namespace hw
 	{
-		CPU::CPU(BUS& bus) : m_bus(bus), m_mmu(m_bus, &m_accessMode)
+		CPU::CPU(BUS& bus) : m_bus(bus)
 		{
 		}
 
 		bool CPU::run(void)
 		{
-			while (!m_halted)
+			// Should probably be moved to Core?
-			{
+			// while (!m_halted)
-				try
+			// {
-				{
+			//     try
-					step(); // fetch + decode + execute one instruction
+			//     {
-				}
+			//         step(); // fetch + decode + execute one instruction
-				catch (const GuestException& e)
+			//     }
-				{
+			//     catch (const GuestException& e)
-					take_exception(e.cause, e.fault_addr);
+			//     {
-				}
+			//         take_exception(e.cause, e.fault_addr);
-			}
+			//     }
+			// }
 			return true;
 		}
 
@@ -54,5 +55,10 @@ namespace dragon
 			// set_interrupts_enabled(false);
 			// m_pc = m_iv;                         // jump to single entry point
 		}
+
+		void CPU::step(void)
+		{
+
+		}
 	}
 }

src/hardware/CPU.hpp

@@ -30,6 +30,36 @@ namespace dragon
 		class BUS;
 		class CPU
 		{
+			public: struct Core
+			{
+				MMU m_mmu;
+				bool m_halted { true };
+
+				std::array<u32, 32> m_gpr;
+				u32 m_pc;
+				u32 m_sp;
+				u32 m_fl;
+				u32 m_mode;
+				u32 m_iv;
+				u32 m_epc;
+				u32 m_cause;
+				u32 m_badaddr;
+				u32 m_estatus;
+				u32 m_scratch;
+				u32 m_ptb;
+				u32 m_asid;
+				u32 m_coreid;
+				u32 m_cycle;
+				u32 m_timer_deadline;
+
+				inline Core(CPU& cpu) : m_mmu(cpu.m_bus, &(cpu.m_accessMode))
+				{
+
+				}
+
+				private:
+			};
+
 			public:
 				CPU(BUS& bus);
 				bool run(void);
@@ -39,10 +69,12 @@ namespace dragon
 				void step(void);
 
 			private:
-				bool m_halted { true };
 				MMUAccessMode m_accessMode { MMUAccessMode::Privileged };
 				BUS& m_bus;
-				MMU m_mmu;
+				Core m_core0 { *this };
+				Core m_core1 { *this };
+				Core m_core2 { *this };
+				Core m_core3 { *this };
 		};
 	}
 }

src/hardware/MMU.hpp

@@ -29,7 +29,7 @@ namespace dragon
 		class MMU : public MemoryDevice
 		{
 			public:
-				explicit MMU(BUS& bus, const MMUAccessMode* mode_ptr);
+				MMU(BUS& bus, const MMUAccessMode* mode_ptr);
 				PhysicalAddress translate(VirtualAddress va, MMUAccessType type, MMUAccessMode mode) const;
 				void enable(bool value = true);
 				void setPtb(PhysicalAddress ptb);