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Added in-place logic opserators + flag operators

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Sylar 2025-03-31 04:23:00 +02:00
parent 702559e907
commit 8565debad1
14 changed files with 195 additions and 18 deletions
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10
.vscode/settings.json vendored
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@ -99,7 +99,8 @@
"format": "cpp",
"stdfloat": "cpp",
"*.inc": "cpp",
"text_encoding": "cpp"
"text_encoding": "cpp",
"__split_buffer": "cpp"
},
"workbench.editorAssociations": {
"*.bin": "hexEditor.hexedit"
@ -156,6 +157,7 @@
"window.zoomLevel": 0,
"explorer.autoReveal": false,
"editor.stickyScroll.enabled": false,
"editor.fontSize": 16,
"workbench.statusBar.visible": false,
"breadcrumbs.enabled": false,
"workbench.tree.enableStickyScroll": false,
@ -170,5 +172,9 @@
"files.eol": "\r\n",
"workbench.iconTheme": "material-icon-theme",
"workbench.colorTheme": "Aramok's GLX Black"
"workbench.colorTheme": "Aramok's GLX Black",
"window.titleBarStyle": "custom",
"window.customTitleBarVisibility": "never"
}

2
build.nr
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@ -1 +1 @@
1619
1620

BIN
extra/dragon/bios.bin
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Binary file not shown.

9
extra/dss/bios/data.dss
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@ -38,6 +38,15 @@
@raw_export_end
@export_comment BIOS_API " --\n"
@export_comment BIOS_API " These are the FLAG addresses."
@raw_export_start BIOS_API
@group Flags
InterruptsEnabled 0x00
OffsetModeEnabled 0x01
@end
@raw_export_end
@export_comment BIOS_API " --\n"
@export_comment BIOS_API " These are the Hardware Interrupt codes of this machine."

6
extra/dss/bios/entry.dss
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@ -25,12 +25,10 @@ _bios_entry_point:
call $_print_machine_info_signle_color ## Print BIOS logo and machine info
## MBR Loading
and FL, 0b1111111111111110 ## Disable interrupts
mov FL, ACC
zflg Flags.InterruptsEnabled ## Disable interrupts
push 0
call $_load_mbr_data_block
or FL, 0b0000000000000001 ## Enable interrupts
mov FL, ACC
sflg Flags.InterruptsEnabled ## Enable interrupts
## ----
%low INST_BIOS_NODE_TOGGLE 0x00 ## Disable BIOS Mode before leaving the BIOS

6
extra/dss/bios/utils.dss
View file

@ -16,15 +16,13 @@ _disk_load_from_ddd_blocking: ## _disk_load_from_ddd_blocking(DiskDriverData* d
addip R1, 2
mov [{MemoryAddresses.DISK_INTERFACE + DiskRegisters.MEMORY_ADDRESS}], *R1
movb [{MemoryAddresses.DISK_INTERFACE + DiskRegisters.SIGNAL}], DiskSignals.START
and FL, 0b1111111111111110 ## Disable interrupts
mov FL, ACC
zflg Flags.InterruptsEnabled ## Disable interrupts
_disk_load_from_ddd_blocking_wait_loop:
## debug_profile_start 0xE0, DBGProfilerTime.MILLIS
mov ACC, [{MemoryAddresses.DISK_INTERFACE + DiskRegisters.RO_STATUS}]
## debug_profile_stop
jne $_disk_load_from_ddd_blocking_wait_loop, DiskStatus.FREE
or FL, 0b0000000000000001 ## Enable interrupts
mov FL, ACC
sflg Flags.InterruptsEnabled ## Enable interrupts
ret

9
extra/dss/bios_api.dss
View file

@ -1,5 +1,5 @@
## --
## -- This file is automatically generated by the DragonAssembler (version 0.4.1617)
## -- This file is automatically generated by the DragonAssembler (version 0.4.1620)
## -- Please do not modify this file in any way.
## --
@ -28,6 +28,13 @@
@end
## --
## These are the FLAG addresses.
@group Flags
InterruptsEnabled 0x00
OffsetModeEnabled 0x01
@end
## --
## These are the Hardware Interrupt codes of this machine.
@group HW_Int
DISK_INTERFACE_FINISHED 0x80

6
extra/info/todo.txt
View file

@ -1,6 +1,4 @@
Runtime:
Add in place logic operators (and, or...) to ExtAlu CPU Extension
Implement native flags operators (set, zero, toggle)
Assembler:
Add subroutine address export functionality
@ -28,4 +26,6 @@ Done:
*Add "Extended mov" instruction set
*Remove old offset mov
*Implelemnt extmov mnemonics in dasm:
*Update Ubuntu install instructions in readme file (for OmniaFramework aswell)
*Update Ubuntu install instructions in readme file (for OmniaFramework aswell)
*Add in place logic operators (and, or...) to ExtAlu CPU Extension
*Implement native flags operators (set, zero, toggle)

74
src/assembler/Assembler.cpp
View file

@ -1171,6 +1171,30 @@ namespace dragon
ostd::String opEdit(lineEdit.new_substr(lineEdit.indexOf(" ") + 1));
opEdit.trim();
int16_t word = 0x0000;
if (STDVEC_CONTAINS(cpuExtensions, "extalu"))
{
if (instEdit == "notip")
{
m_code.push_back(data::OpCodes::Ext02);
eOperandType opType = parseOperand(opEdit, word);
if (opType != eOperandType::Register)
{
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Register required\n";
exit(0);
return;
}
m_code.push_back(hw::cpuext::ExtAlu::OpCodes::notip_reg);
m_code.push_back((uint8_t)word);
return;
}
}
else if (instEdit == "notip")
{
std::cout << "ExtAlu instruction detected, please add '--extalu' flag to dasm.\n";
exit(0);
return;
}
if (instEdit == "inc")
{
eOperandType opType = parseOperand(opEdit, word);
@ -1337,6 +1361,45 @@ namespace dragon
m_code.push_back((uint8_t)word);
return;
}
else if (instEdit == "zflg")
{
eOperandType opType = parseOperand(opEdit, word);
if (opType != eOperandType::Immediate)
{
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Immediate required\n";
exit(0);
return;
}
m_code.push_back(data::OpCodes::ZeroFlag);
m_code.push_back((uint8_t)word);
return;
}
else if (instEdit == "sflg")
{
eOperandType opType = parseOperand(opEdit, word);
if (opType != eOperandType::Immediate)
{
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Immediate required\n";
exit(0);
return;
}
m_code.push_back(data::OpCodes::SetFlag);
m_code.push_back((uint8_t)word);
return;
}
else if (instEdit == "tflg")
{
eOperandType opType = parseOperand(opEdit, word);
if (opType != eOperandType::Immediate)
{
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Immediate required\n";
exit(0);
return;
}
m_code.push_back(data::OpCodes::ToggleFlag);
m_code.push_back((uint8_t)word);
return;
}
else
{
std::cout << "Unknown instruction; " << line << " (" << instEdit << ")\n";
@ -1356,7 +1419,7 @@ namespace dragon
if (STDVEC_CONTAINS(cpuExtensions, "extalu"))
{
auto st = opEdit.tokenize(",");
if (instEdit == "addipu" || instEdit == "subipu" || instEdit == "mulipu" || instEdit == "divipu" || instEdit == "addip" || instEdit == "subip" || instEdit == "mulip" || instEdit == "divip")
if (instEdit == "addipu" || instEdit == "subipu" || instEdit == "mulipu" || instEdit == "divipu" || instEdit == "addip" || instEdit == "subip" || instEdit == "mulip" || instEdit == "divip" || instEdit == "orip" || instEdit == "andip" || instEdit == "xorip")
{
m_code.push_back(data::OpCodes::Ext02);
m_code.push_back(0x00);
@ -1380,6 +1443,9 @@ namespace dragon
else if (instEdit == "subipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::subipu_imm_in_reg;
else if (instEdit == "mulipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::mulipu_imm_in_reg;
else if (instEdit == "divipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::divipu_imm_in_reg;
else if (instEdit == "orip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::orip_imm_in_reg;
else if (instEdit == "andip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::andip_imm_in_reg;
else if (instEdit == "xorip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::xorip_imm_in_reg;
m_code.push_back((uint8_t)((word & 0xFF00) >> 8));
m_code.push_back((uint8_t)(word & 0x00FF));
}
@ -1393,6 +1459,9 @@ namespace dragon
else if (instEdit == "subipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::subipu_reg_in_reg;
else if (instEdit == "mulipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::mulipu_reg_in_reg;
else if (instEdit == "divipu") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::divipu_reg_in_reg;
else if (instEdit == "orip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::orip_reg_in_reg;
else if (instEdit == "andip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::andip_reg_in_reg;
else if (instEdit == "xorip") m_code[m_code.size() - 2] = hw::cpuext::ExtAlu::OpCodes::xorip_reg_in_reg;
m_code.push_back((uint8_t)word);
}
else
@ -1404,7 +1473,8 @@ namespace dragon
return;
}
}
else if (instEdit == "addipu" || instEdit == "subipu" || instEdit == "mulipu" || instEdit == "divipu" || instEdit == "addip" || instEdit == "subip" || instEdit == "mulip" || instEdit == "divip")
else if (instEdit == "addipu" || instEdit == "subipu" || instEdit == "mulipu" || instEdit == "divipu" || instEdit == "addip" || instEdit == "subip" || instEdit == "mulip" || instEdit == "divip"
|| instEdit == "orip" || instEdit == "andip" || instEdit == "xorip" || instEdit == "notip")
{
std::cout << "ExtAlu instruction detected, please add '--extalu' flag to dasm.\n";
exit(0);

58
src/hardware/CPUExtensions.cpp
View file

@ -681,6 +681,64 @@ namespace dragon
vcpu.writeRegister16(data::Registers::RV, rv);
}
break;
case OpCodes::andip_reg_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint8_t src_reg = vcpu.fetch8();
int16_t src_val = vcpu.readRegister(src_reg);
int16_t dest_val = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, src_val & dest_val);
}
break;
case OpCodes::andip_imm_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint16_t src_val = vcpu.fetch16();
int16_t value = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, value & src_val);
}
break;
case OpCodes::orip_reg_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint8_t src_reg = vcpu.fetch8();
int16_t src_val = vcpu.readRegister(src_reg);
int16_t dest_val = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, src_val | dest_val);
}
break;
case OpCodes::orip_imm_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint16_t src_val = vcpu.fetch16();
int16_t value = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, value | src_val);
}
break;
case OpCodes::xorip_reg_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint8_t src_reg = vcpu.fetch8();
int16_t src_val = vcpu.readRegister(src_reg);
int16_t dest_val = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, src_val ^ dest_val);
}
break;
case OpCodes::xorip_imm_in_reg:
{
uint8_t dest_reg = vcpu.fetch8();
uint16_t src_val = vcpu.fetch16();
int16_t value = vcpu.readRegister(dest_reg);
vcpu.writeRegister16(dest_reg, value ^ src_val);
}
break;
case OpCodes::notip_reg:
{
uint8_t regAddr = vcpu.fetch8();
int16_t value = vcpu.readRegister(regAddr);
vcpu.writeRegister16(regAddr, ~value);
}
break;
default:
{
//TODO: Error

9
src/hardware/CPUExtensions.hpp
View file

@ -82,6 +82,15 @@ namespace dragon
inline static constexpr uint8_t mulip_imm_in_reg = 0x25;
inline static constexpr uint8_t divip_reg_in_reg = 0x26;
inline static constexpr uint8_t divip_imm_in_reg = 0x27;
inline static constexpr uint8_t andip_reg_in_reg = 0x30;
inline static constexpr uint8_t andip_imm_in_reg = 0x31;
inline static constexpr uint8_t orip_reg_in_reg = 0x32;
inline static constexpr uint8_t orip_imm_in_reg = 0x33;
inline static constexpr uint8_t xorip_reg_in_reg = 0x34;
inline static constexpr uint8_t xorip_imm_in_reg = 0x35;
inline static constexpr uint8_t notip_reg = 0x36;
};
public:
inline ExtAlu(void) : data::CPUExtension(data::OpCodes::Ext02, "extalu") { }

19
src/hardware/VirtualCPU.cpp
View file

@ -839,6 +839,25 @@ namespace dragon
m_subroutineCounter++;
}
break;
case data::OpCodes::ZeroFlag:
{
uint8_t flag = fetch8();
setFlag(flag, false);
}
break;
case data::OpCodes::SetFlag:
{
uint8_t flag = fetch8();
setFlag(flag, true);
}
break;
case data::OpCodes::ToggleFlag:
{
uint8_t flag = fetch8();
bool value = readFlag(flag);
setFlag(flag, !value);
}
break;
case data::OpCodes::Ext01:
case data::OpCodes::Ext02:
case data::OpCodes::Ext03:

3
src/tools/GlobalData.hpp
View file

@ -374,6 +374,9 @@ namespace dragon
inline static constexpr uint8_t Ext15 = 0xEE;
inline static constexpr uint8_t Ext16 = 0xEF;
inline static constexpr uint8_t ZeroFlag = 0xF0;
inline static constexpr uint8_t SetFlag = 0xF1;
inline static constexpr uint8_t ToggleFlag = 0xF2;
inline static constexpr uint8_t RetInt = 0xFD;
inline static constexpr uint8_t Int = 0xFE;
inline static constexpr uint8_t Halt = 0xFF;

2
src/tools/Tools.cpp
View file

@ -128,7 +128,7 @@ namespace dragon
index++;
}
vHDD.unmount();
out.nl().fg(ostd::ConsoleColors::Green).p("Success. Data writte to Virtual Disk:").nl();
out.nl().fg(ostd::ConsoleColors::Green).p("Success. Data written to Virtual Disk:").nl();
out.p(" Data Path: ").p(data_file.cpp_str()).nl();
out.p(" Disk Path: ").p(vdisk_file.cpp_str()).nl();
out.p(" Data Address: ").p(ostd::Utils::getHexStr(addr, true, 4).cpp_str()).nl();