Completed and tested ExtMov CPU extension implementation
This commit is contained in:
parent
522e31ec22
commit
c851940762
14 changed files with 1374 additions and 165 deletions
16
.vscode/settings.json
vendored
16
.vscode/settings.json
vendored
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@ -96,7 +96,11 @@
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"stacktrace": "cpp",
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"*.ipp": "cpp",
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"format": "cpp",
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"stdfloat": "cpp"
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"stdfloat": "cpp",
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"*.dss": "python"
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},
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"workbench.editorAssociations": {
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"*.bin": "hexEditor.hexedit"
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},
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"workbench.colorCustomizations": {
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@ -112,7 +116,7 @@
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"editorBracketMatch.background": "#444",
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"editorBracketMatch.border": "#b80318",
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"editor.selectionBackground": "#3b3b3b",
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"editor.selectionHighlightBackground": "#702900",
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"editor.selectionHighlightBackground": "#702900e8",
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"statusBar.background": "#2e2850",
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"minimap.background" : "#1b1b1b",
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"sideBar.background": "#1b1b1b"
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@ -146,7 +150,7 @@
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"workbench.editor.openPositioning": "last",
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"workbench.editor.tabActionCloseVisibility": false,
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"window.density.editorTabHeight": "compact",
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"window.zoomLevel": 1,
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"window.zoomLevel": 0,
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"explorer.autoReveal": false,
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"editor.stickyScroll.enabled": false,
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"workbench.statusBar.visible": false,
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@ -156,5 +160,9 @@
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"cmake.configureOnOpen": false,
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"cmake.options.statusBarVisibility": "hidden",
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"git.openRepositoryInParentFolders": "never"
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"git.openRepositoryInParentFolders": "never",
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"python.languageServer": "None",
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"files.eol": "\r\n"
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}
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2
build.nr
2
build.nr
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@ -1 +1 @@
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1587
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1588
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@ -1,51 +1,60 @@
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Text visualization for hardware interrupts (in call-tree view)
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Inverted Colors in Text-Single-Color
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show where interrupts are disabled (in call-tree view)
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***Add possibility to specify instruction sets in machine config
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#***Add possibility to specify instruction sets in machine config
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Add possibility to specify required instruction sets in dasm
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Add "Extended mov" instruction set
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Remove old offset mov
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Implelemnt Instructions:
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#***Add "Extended mov" instruction set
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#***Remove old offset mov
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Implelemnt Instructions in dasm:
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## Offset on first operand
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omov *R1, 0xFAAB, 4 ## Move word immediate into (deref reg + immediate offset word)
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omov *R1, 0xFAAB, R10 ## Move word immediate into (deref reg + reg offset)
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omov *R1, 0xFAAB, 4 ## Move word immediate into (deref reg + immediate offset byte)
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omovb *R1, 0xFA, 4 ## Move byte immediate into (deref reg + immediate offset word)
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omovb *R1, 0xFA, R10 ## Move byte immediate into (deref reg + reg offset)
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omovb *R1, 0xFA, 4 ## Move byte immediate into (deref reg + immediate offset byte)
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omov *R1, *R2, 4 ## Move word deref reg into (deref reg + immediate offset word)
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omov *R1, *R2, R10 ## Move word deref reg into (deref reg + reg offset)
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omov *R1, *R2, 4 ## Move word deref reg into (deref reg + immediate offset byte)
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omovb *R1, *R2, 4 ## Move byte deref reg into (deref reg + immediate offset word)
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omovb *R1, *R2, R10 ## Move byte deref reg into (deref reg + reg offset)
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omov R1, [0xFAAB], 4 ## Move word Memory into (reg + immediate offset word)
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omov R1, [0xFAAB], R10 ## Move word Memory into (reg + reg offset)
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omovb R1, [0xFAAB], 4 ## Move byte Memory into (reg + immediate offset word)
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omovb R1, [0xFAAB], R10 ## Move byte Memory into (reg + reg offset)
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omov R1, *R2, 4 ## Move word deref reg into (reg + immediate offset word)
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omov R1, *R2, R10 ## Move word deref reg into (reg + reg offset)
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omovb R1, *R2, 4 ## Move byte deref reg into (reg + immediate offset word)
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omovb R1, *R2, R10 ## Move byte deref reg into (reg + reg offset)
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omovb *R1, *R2, 4 ## Move byte deref reg into (deref reg + immediate offset byte)
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omov [0x1800], 0xACAB, 4 ## Move word immediate into (Memory + immediate offset word)
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omov [0x1800], 0xACAB, R10 ## Move word immediate into (Memory + reg offset)
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omov [0x1800], 0xACAB, 4 ## Move word immediate into (Memory + immediate offset byte)
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omovb [0x1800], 0xAC, 4 ## Move byte immediate into (Memory + immediate offset word)
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omovb [0x1800], 0xAC, R10 ## Move byte immediate into (Memory + reg offset)
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omovb [0x1800], 0xAC, 4 ## Move byte immediate into (Memory + immediate offset byte)
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## Offset on second operand
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movo *R1, *R2, 4 ## Move word (deref reg + immediate offset word) into deref reg
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movo *R1, *R2, R10 ## Move word (deref reg + reg offset) into deref reg
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movo *R1, *R2, 4 ## Move word (deref reg + immediate offset byte) into deref reg
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movbo *R1, *R2, 4 ## Move byte (deref reg + immediate offset word) into deref reg
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movbo *R1, *R2, R10 ## Move byte (deref reg + reg offset) into deref reg
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movbo *R1, *R2, 4 ## Move byte (deref reg + immediate offset byte) into deref reg
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movo R1, [0xFAAB], 4 ## Move word (Memory + immediate offset word) into reg
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movo R1, [0xFAAB], R10 ## Move word (Memory + reg offset) into reg
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movo R1, [0xFAAB], 4 ## Move word (Memory + immediate offset byte) into reg
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movbo R1, [0xFAAB], 4 ## Move byte (Memory + immediate offset word) into reg
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movbo R1, [0xFAAB], R10 ## Move byte (Memory + reg offset) into reg
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movbo R1, [0xFAAB], 4 ## Move byte (Memory + immediate offset byte) into reg
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movo R1, *R2, 4 ## Move word (deref reg + immediate offset word) into reg
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movo R1, *R2, R10 ## Move word (deref reg + reg offset) into reg
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movo R1, *R2, 4 ## Move word (deref reg + immediate offset byte) into reg
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movbo R1, *R2, 4 ## Move byte (deref reg + immediate offset word) into reg
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movbo R1, *R2, R10 ## Move byte (deref reg + reg offset) into reg
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## Plus every (immediate offset) variant with byte offset instead of word offset
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movbo R1, *R2, 4 ## Move byte (deref reg + immediate offset byte) into reg
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714
extra/dss/extmov_unit_tests.dss
Normal file
714
extra/dss/extmov_unit_tests.dss
Normal file
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@ -0,0 +1,714 @@
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.load 0x1740
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@define EXT_MOV 0xE0
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@define wimm_in_dreg_immoffw 0x10
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@define wimm_in_dreg_regoff 0x11
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@define wimm_in_dreg_immoffb 0x12
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@define bimm_in_dreg_immoffw 0x13
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@define bimm_in_dreg_regoff 0x14
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@define bimm_in_dreg_immoffb 0x15
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@define wdreg_in_dreg_immoffw 0x16
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@define wdreg_in_dreg_regoff 0x17
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@define wdreg_in_dreg_immoffb 0x18
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@define bdreg_in_dreg_immoffw 0x19
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@define bdreg_in_dreg_regoff 0x1A
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@define bdreg_in_dreg_immoffb 0x1B
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@define wimm_in_mem_immoffw 0x30
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@define wimm_in_mem_regoff 0x31
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@define wimm_in_mem_immoffb 0x32
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@define bimm_in_mem_immoffw 0x33
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@define bimm_in_mem_regoff 0x34
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@define bimm_in_mem_immoffb 0x35
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@define wdreg_immoffw_in_dreg 0x40
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@define wdreg_regoff_in_dreg 0x41
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@define wdreg_immoffb_in_dreg 0x42
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@define bdreg_immoffw_in_dreg 0x43
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@define bdreg_regoff_in_dreg 0x44
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@define bdreg_immoffb_in_dreg 0x45
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@define wmem_immoffw_in_reg 0x50
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@define wmem_regoff_in_reg 0x51
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@define wmem_immoffb_in_reg 0x52
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@define bmem_immoffw_in_reg 0x53
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@define bmem_regoff_in_reg 0x54
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@define bmem_immoffb_in_reg 0x55
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@define wdreg_immoffw_in_reg 0x56
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@define wdreg_regoff_in_reg 0x57
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@define wdreg_immoffb_in_reg 0x58
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@define bdreg_immoffw_in_reg 0x59
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@define bdreg_regoff_in_reg 0x5A
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@define bdreg_immoffb_in_reg 0x5B
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@define _IP 0x00
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@define _SP 0x01
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@define _FP 0x02
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@define _RV 0x03
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@define _PP 0x04
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@define _FL 0x05
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@define _ACC 0x06
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@define _S1 0x07
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@define _S2 0x08
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@define _S3 0x09
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@define _R1 0x0A
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@define _R2 0x0B
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@define _R3 0x0C
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@define _R4 0x0D
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@define _R5 0x0E
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@define _R6 0x0F
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@define _R7 0x10
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@define _R8 0x11
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@define _R9 0x12
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@define _R10 0x13
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.code
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mov R5, 0x00 ## R5 is the test counter
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mov R6, 0x00 ## R6 is used as flag set if one test fails
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mov R10, 0xE0 ## Clear the screen
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int 0x30 ## --
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## debug_break
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## ------ Test 1 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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%low EXT_MOV wimm_in_dreg_immoffw _R1 0xFA 0xAA 0x00 0x02
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add R1, 0x02
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mov R1, ACC
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mov ACC, *R1
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jeq $test_1_passed, 0xFAAA
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push 0
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call $test_failed
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inc R6
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test_1_passed:
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## ------ Test 2 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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mov R2, 0x03
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%low EXT_MOV wimm_in_dreg_regoff _R1 0xFA 0xAA _R2
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add R1, 0x03
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mov R1, ACC
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mov ACC, *R1
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jeq $test_2_passed, 0xFAAA
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push 0
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call $test_failed
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inc R6
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test_2_passed:
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## ------ Test 3 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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%low EXT_MOV wimm_in_dreg_immoffb _R1 0xFA 0xAA 0x04
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add R1, 0x04
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mov R1, ACC
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mov ACC, *R1
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jeq $test_3_passed, 0xFAAA
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push 0
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call $test_failed
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inc R6
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test_3_passed:
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## ------ Test 4 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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%low EXT_MOV bimm_in_dreg_immoffw _R1 0xEE 0x00 0x06
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add R1, 0x06
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mov R1, ACC
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movb ACC, *R1
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jeq $test_4_passed, 0xEE
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push 0
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call $test_failed
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inc R6
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test_4_passed:
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## ------ Test 5 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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mov R2, 0x06
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%low EXT_MOV bimm_in_dreg_regoff _R1 0x11 _R2
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add R1, 0x06
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mov R1, ACC
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movb ACC, *R1
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jeq $test_5_passed, 0x11
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push 0
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call $test_failed
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inc R6
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test_5_passed:
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## ------ Test 6 ------
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## debug_break
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inc R5
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mov R1, 0x3000
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%low EXT_MOV bimm_in_dreg_immoffb _R1 0x22 0x08
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add R1, 0x08
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mov R1, ACC
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movb ACC, *R1
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jeq $test_6_passed, 0x22
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push 0
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call $test_failed
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inc R6
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test_6_passed:
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## ------ Test 7 ------
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## debug_break
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inc R5
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mov R1, 0x5000
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mov R3, 0x4000
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mov *R3, 0x33
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%low EXT_MOV wdreg_in_dreg_immoffw _R1 _R3 0x00 0x0A
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add R1, 0x0A
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mov R1, ACC
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mov ACC, *R1
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jeq $test_7_passed, 0x33
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push 0
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call $test_failed
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inc R6
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test_7_passed:
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## ------ Test 8 ------
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## debug_break
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inc R5
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mov R1, 0x5000
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mov R3, 0x4000
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mov *R3, 0x44
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mov R2, 0x0C
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%low EXT_MOV wdreg_in_dreg_regoff _R1 _R3 _R2
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add R1, 0x0C
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mov R1, ACC
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mov ACC, *R1
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jeq $test_8_passed, 0x44
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push 0
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call $test_failed
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inc R6
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test_8_passed:
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## ------ Test 9 ------
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## debug_break
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inc R5
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mov R1, 0x5000
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mov R3, 0x4000
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mov *R3, 0x55
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%low EXT_MOV wdreg_in_dreg_immoffb _R1 _R3 0x0E
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add R1, 0x0E
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mov R1, ACC
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mov ACC, *R1
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jeq $test_9_passed, 0x55
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push 0
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call $test_failed
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inc R6
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test_9_passed:
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## ------ Test 10 ------
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## debug_break
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inc R5
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mov R1, 0x6000
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mov R3, 0x5000
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movb *R3, 0x66
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%low EXT_MOV bdreg_in_dreg_immoffw _R1 _R3 0x00 0x10
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add R1, 0x10
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mov R1, ACC
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movb ACC, *R1
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jeq $test_10_passed, 0x66
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push 0
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call $test_failed
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inc R6
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test_10_passed:
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## ------ Test 11 ------
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## debug_break
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inc R5
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mov R1, 0x6000
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mov R3, 0x5000
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movb *R3, 0x77
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mov R2, 0x12
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%low EXT_MOV bdreg_in_dreg_regoff _R1 _R3 _R2
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add R1, 0x12
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mov R1, ACC
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movb ACC, *R1
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jeq $test_11_passed, 0x77
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push 0
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call $test_failed
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inc R6
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test_11_passed:
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## ------ Test 12 ------
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## debug_break
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inc R5
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mov R1, 0x6000
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mov R3, 0x5000
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movb *R3, 0x88
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%low EXT_MOV bdreg_in_dreg_immoffb _R1 _R3 0x14
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add R1, 0x14
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mov R1, ACC
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movb ACC, *R1
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jeq $test_12_passed, 0x88
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push 0
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call $test_failed
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inc R6
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test_12_passed:
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## ------ Test 13 ------
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## debug_break
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inc R5
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%low EXT_MOV wimm_in_mem_immoffw 0x70 0x00 0xAA 0x99 0x00 0x16
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mov R1, 0x7000
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add R1, 0x16
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mov R1, ACC
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mov ACC, *R1
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jeq $test_13_passed, 0xAA99
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push 0
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call $test_failed
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inc R6
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test_13_passed:
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## ------ Test 14 ------
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## debug_break
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inc R5
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mov R2, 0x18
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%low EXT_MOV wimm_in_mem_regoff 0x70 0x00 0xAA 0xAA _R2
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mov R1, 0x7000
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add R1, 0x18
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mov R1, ACC
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mov ACC, *R1
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jeq $test_14_passed, 0xAAAA
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push 0
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call $test_failed
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inc R6
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test_14_passed:
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## ------ Test 15 ------
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## debug_break
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inc R5
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%low EXT_MOV wimm_in_mem_immoffb 0x70 0x00 0xAA 0xBB 0x1A
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mov R1, 0x7000
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add R1, 0x1A
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mov R1, ACC
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mov ACC, *R1
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jeq $test_15_passed, 0xAABB
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push 0
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call $test_failed
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inc R6
|
||||
test_15_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 16 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
%low EXT_MOV bimm_in_mem_immoffw 0x80 0x00 0xCC 0x00 0x1C
|
||||
mov R1, 0x8000
|
||||
add R1, 0x1C
|
||||
mov R1, ACC
|
||||
movb ACC, *R1
|
||||
jeq $test_16_passed, 0xCC
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_16_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 17 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R2, 0x1E
|
||||
%low EXT_MOV bimm_in_mem_regoff 0x80 0x00 0xDD _R2
|
||||
mov R1, 0x8000
|
||||
add R1, 0x1E
|
||||
mov R1, ACC
|
||||
movb ACC, *R1
|
||||
jeq $test_17_passed, 0xDD
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_17_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 18 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
%low EXT_MOV bimm_in_mem_immoffb 0x80 0x00 0xEE 0x20
|
||||
mov R1, 0x8000
|
||||
add R1, 0x20
|
||||
mov R1, ACC
|
||||
movb ACC, *R1
|
||||
jeq $test_18_passed, 0xEE
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_18_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 19 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0x9000
|
||||
mov R3, 0xA000
|
||||
mov [0xA022], 0x66
|
||||
%low EXT_MOV wdreg_immoffw_in_dreg _R1 _R3 0x00 0x22
|
||||
mov ACC, *R1
|
||||
jeq $test_19_passed, 0x66
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_19_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 20 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0x9000
|
||||
mov R3, 0xA000
|
||||
mov [0xA033], 0x77
|
||||
mov R2, 0x33
|
||||
%low EXT_MOV wdreg_regoff_in_dreg _R1 _R3 _R2
|
||||
mov ACC, *R1
|
||||
jeq $test_20_passed, 0x77
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_20_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 21 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0x9000
|
||||
mov R3, 0xA000
|
||||
mov [0xA044], 0x88
|
||||
%low EXT_MOV wdreg_immoffb_in_dreg _R1 _R3 0x44
|
||||
mov ACC, *R1
|
||||
jeq $test_21_passed, 0x88
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_21_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 22 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0xA000
|
||||
mov R3, 0xB000
|
||||
movb [0xB055], 0x99
|
||||
%low EXT_MOV bdreg_immoffw_in_dreg _R1 _R3 0x00 0x55
|
||||
movb ACC, *R1
|
||||
jeq $test_22_passed, 0x99
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_22_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 23 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0xA000
|
||||
mov R3, 0xB000
|
||||
movb [0xB066], 0xAA
|
||||
mov R2, 0x66
|
||||
%low EXT_MOV bdreg_regoff_in_dreg _R1 _R3 _R2
|
||||
movb ACC, *R1
|
||||
jeq $test_23_passed, 0xAA
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_23_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 24 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R1, 0xA000
|
||||
mov R3, 0xB000
|
||||
movb [0xB077], 0xBB
|
||||
%low EXT_MOV bdreg_immoffb_in_dreg _R1 _R3 0x77
|
||||
movb ACC, *R1
|
||||
jeq $test_24_passed, 0xBB
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_24_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 25 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov [0xC088], 0xCC
|
||||
%low EXT_MOV wmem_immoffw_in_reg _R1 0xC0 0x00 0x00 0x88
|
||||
mov ACC, R1
|
||||
jeq $test_25_passed, 0xCC
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_25_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 26 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov [0xC099], 0xDD
|
||||
mov R2, 0x99
|
||||
%low EXT_MOV wmem_regoff_in_reg _R1 0xC0 0x00 _R2
|
||||
mov ACC, R1
|
||||
jeq $test_26_passed, 0xDD
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_26_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 27 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov [0xC0AA], 0xEE
|
||||
%low EXT_MOV wmem_immoffb_in_reg _R1 0xC0 0x00 0xAA
|
||||
mov ACC, R1
|
||||
jeq $test_27_passed, 0xEE
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_27_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 28 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
movb [0xD099], 0x11
|
||||
%low EXT_MOV bmem_immoffw_in_reg _R1 0xD0 0x00 0x00 0x99
|
||||
mov ACC, R1
|
||||
jeq $test_28_passed, 0x11
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_28_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 29 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
movb [0xD0AA], 0x22
|
||||
mov R2, 0xAA
|
||||
%low EXT_MOV bmem_regoff_in_reg _R1 0xD0 0x00 _R2
|
||||
mov ACC, R1
|
||||
jeq $test_29_passed, 0x22
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_29_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 30 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
movb [0xD0BB], 0x33
|
||||
%low EXT_MOV bmem_immoffb_in_reg _R1 0xD0 0x00 0xBB
|
||||
mov ACC, R1
|
||||
jeq $test_30_passed, 0x33
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_30_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 31 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x4000
|
||||
mov [0x40CC], 0x44
|
||||
%low EXT_MOV wdreg_immoffw_in_reg _R1 _R3 0x00 0xCC
|
||||
mov ACC, R1
|
||||
jeq $test_31_passed, 0x44
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_31_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 32 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x4000
|
||||
mov [0x40DD], 0x55
|
||||
mov R2, 0xDD
|
||||
%low EXT_MOV wdreg_regoff_in_reg _R1 _R3 _R2
|
||||
mov ACC, R1
|
||||
jeq $test_32_passed, 0x55
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_32_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 33 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x4000
|
||||
mov [0x40EE], 0x66
|
||||
%low EXT_MOV wdreg_immoffb_in_reg _R1 _R3 0xEE
|
||||
mov ACC, R1
|
||||
jeq $test_33_passed, 0x66
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_33_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 34 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x5000
|
||||
movb [0x5011], 0x77
|
||||
%low EXT_MOV bdreg_immoffw_in_reg _R1 _R3 0x00 0x11
|
||||
mov ACC, R1
|
||||
jeq $test_34_passed, 0x77
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_34_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 35 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x5000
|
||||
movb [0x5022], 0x88
|
||||
mov R2, 0x22
|
||||
%low EXT_MOV bdreg_regoff_in_reg _R1 _R3 _R2
|
||||
mov ACC, R1
|
||||
jeq $test_35_passed, 0x88
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_35_passed:
|
||||
|
||||
|
||||
|
||||
## ------ Test 36 ------
|
||||
## debug_break
|
||||
inc R5
|
||||
mov R3, 0x5000
|
||||
movb [0x5033], 0x99
|
||||
%low EXT_MOV bdreg_immoffb_in_reg _R1 _R3 0x33
|
||||
mov ACC, R1
|
||||
jeq $test_36_passed, 0x99
|
||||
push 0
|
||||
call $test_failed
|
||||
inc R6
|
||||
test_36_passed:
|
||||
|
||||
|
||||
|
||||
|
||||
## ------- END -------
|
||||
debug_break
|
||||
movb ACC, [$test_count]
|
||||
sub ACC, R6
|
||||
mov R6, ACC
|
||||
mov R10, 0x03
|
||||
mov R9, $tests_pass_str
|
||||
int 0x30
|
||||
mov R10, 0x01
|
||||
mov R9, 32
|
||||
int 0x30
|
||||
mov R10, 0x04
|
||||
mov R9, R6
|
||||
int 0x30
|
||||
mov R10, 0x01
|
||||
mov R9, 47
|
||||
int 0x30
|
||||
mov R10, 0x04
|
||||
movb R9, [$test_count]
|
||||
int 0x30
|
||||
mov R10, 0x02
|
||||
int 0x30
|
||||
end:
|
||||
jmp $end
|
||||
hlt
|
||||
|
||||
|
||||
|
||||
test_failed:
|
||||
mov R10, 0x03
|
||||
mov R9, $test_fail_str
|
||||
int 0x30
|
||||
mov R10, 0x01
|
||||
mov R9, 32
|
||||
int 0x30
|
||||
mov R10, 0x04
|
||||
mov R9, R5
|
||||
int 0x30
|
||||
mov R10, 0x02
|
||||
int 0x30
|
||||
ret
|
||||
|
||||
|
||||
.data
|
||||
$test_fail_str "FAIL: Test"
|
||||
$tests_pass_str "Tests passed:"
|
||||
$test_count 36
|
||||
|
|
@ -17,9 +17,11 @@ if [ $? -eq 0 ]; then
|
|||
/bin/bash ./load_mbr
|
||||
cd ..
|
||||
printf "${green}Compiling Test Program...\n"
|
||||
./dasm dss/newTest.dss -o newTest.bin --save-disassembly disassembly/newTest.dds --verbose
|
||||
./dasm dss/extmov_unit_tests.dss -o extmov_unit_tests.bin --save-disassembly disassembly/extmov_unit_tests.dds --verbose
|
||||
# ./dasm dss/newTest.dss -o newTest.bin --save-disassembly disassembly/newTest.dds --verbose
|
||||
printf "\n${green}Running Application...\n\n${clear}"
|
||||
./ddb config/testMachine.dvm --force-load newTest.bin 0x00 --verbose-load
|
||||
./ddb config/testMachine.dvm --force-load extmov_unit_tests.bin 0x00 --verbose-load
|
||||
# ./ddb config/testMachine.dvm --force-load newTest.bin 0x00 --verbose-load
|
||||
cp dragon/disk1.dr ../extra/dragon/disk1.dr
|
||||
cp dragon/cmos.dr ../extra/dragon/cmos.dr
|
||||
fi
|
||||
|
|
|
|||
|
|
@ -17,9 +17,11 @@ if [ $? -eq 0 ]; then
|
|||
/bin/bash ./load_mbr
|
||||
cd ..
|
||||
printf "${green}Compiling Test Program...\n"
|
||||
./dasm dss/newTest.dss -o newTest.bin --save-disassembly disassembly/newTest.dds --verbose
|
||||
./dasm dss/extmov_unit_tests.dss -o extmov_unit_tests.bin --save-disassembly disassembly/extmov_unit_tests.dds --verbose
|
||||
# ./dasm dss/newTest.dss -o newTest.bin --save-disassembly disassembly/newTest.dds --verbose
|
||||
printf "\n${green}Running Application...\n\n${clear}"
|
||||
./dvm config/testMachine.dvm --force-load newTest.bin 0x00
|
||||
./dvm config/testMachine.dvm --force-load extmov_unit_tests.bin 0x00
|
||||
# ./dvm config/testMachine.dvm --force-load newTest.bin 0x00
|
||||
cp dragon/disk1.dr ../extra/dragon/disk1.dr
|
||||
cp dragon/cmos.dr ../extra/dragon/cmos.dr
|
||||
fi
|
||||
|
|
|
|||
|
|
@ -173,6 +173,9 @@ namespace dragon
|
|||
tmpCommand = "--save-exports";
|
||||
tmpCommand.addRightPadding(commandLength);
|
||||
out.fg(ostd::ConsoleColors::Blue).p(tmpCommand).fg(ostd::ConsoleColors::Green).p("Used to save any specified exports in the code.").reset().nl();
|
||||
tmpCommand = "--extmov";
|
||||
tmpCommand.addRightPadding(commandLength);
|
||||
out.fg(ostd::ConsoleColors::Blue).p(tmpCommand).fg(ostd::ConsoleColors::Green).p("Enables the <extmov> CPU extension.").reset().nl();
|
||||
tmpCommand = "--help";
|
||||
tmpCommand.addRightPadding(commandLength);
|
||||
out.fg(ostd::ConsoleColors::Blue).p(tmpCommand).fg(ostd::ConsoleColors::Green).p("Displays this help message.").reset().nl();
|
||||
|
|
@ -1616,48 +1619,48 @@ namespace dragon
|
|||
|
||||
void Assembler::parse3Operand(ostd::String line)
|
||||
{
|
||||
ostd::String lineEdit(line);
|
||||
ostd::String instEdit(lineEdit.new_substr(0, lineEdit.indexOf(" ")));
|
||||
instEdit.trim().toLower();
|
||||
ostd::String opEdit(lineEdit.new_substr(lineEdit.indexOf(" ") + 1));
|
||||
opEdit.trim();
|
||||
int16_t word = 0x0000;
|
||||
if (instEdit == "mov")
|
||||
{
|
||||
auto st = opEdit.tokenize(",");
|
||||
eOperandType opType = parseOperand(st.next(), word);
|
||||
if (opType != eOperandType::Register)
|
||||
{
|
||||
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Register required\n";
|
||||
exit(0);
|
||||
return;
|
||||
}
|
||||
m_code.push_back(data::OpCodes::MovImmRegOffReg);
|
||||
m_code.push_back((uint8_t)word);
|
||||
opType = parseOperand(st.next(), word);
|
||||
if (opType != eOperandType::DerefMemory)
|
||||
{
|
||||
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Pointer required\n";
|
||||
exit(0);
|
||||
return;
|
||||
}
|
||||
m_code.push_back((uint8_t)((word & 0xFF00) >> 8));
|
||||
m_code.push_back((uint8_t)(word & 0x00FF));
|
||||
opType = parseOperand(st.next(), word);
|
||||
if (opType != eOperandType::Register)
|
||||
{
|
||||
std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Register required\n";
|
||||
exit(0);
|
||||
return;
|
||||
}
|
||||
m_code.push_back((uint8_t)word);
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
std::cout << "Unknown instruction; " << line << " (" << instEdit << ")\n";
|
||||
exit(0);
|
||||
}
|
||||
// ostd::String lineEdit(line);
|
||||
// ostd::String instEdit(lineEdit.new_substr(0, lineEdit.indexOf(" ")));
|
||||
// instEdit.trim().toLower();
|
||||
// ostd::String opEdit(lineEdit.new_substr(lineEdit.indexOf(" ") + 1));
|
||||
// opEdit.trim();
|
||||
// int16_t word = 0x0000;
|
||||
// if (instEdit == "mov")
|
||||
// {
|
||||
// auto st = opEdit.tokenize(",");
|
||||
// eOperandType opType = parseOperand(st.next(), word);
|
||||
// if (opType != eOperandType::Register)
|
||||
// {
|
||||
// std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Register required\n";
|
||||
// exit(0);
|
||||
// return;
|
||||
// }
|
||||
// m_code.push_back(data::OpCodes::MovImmRegOffReg);
|
||||
// m_code.push_back((uint8_t)word);
|
||||
// opType = parseOperand(st.next(), word);
|
||||
// if (opType != eOperandType::DerefMemory)
|
||||
// {
|
||||
// std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Pointer required\n";
|
||||
// exit(0);
|
||||
// return;
|
||||
// }
|
||||
// m_code.push_back((uint8_t)((word & 0xFF00) >> 8));
|
||||
// m_code.push_back((uint8_t)(word & 0x00FF));
|
||||
// opType = parseOperand(st.next(), word);
|
||||
// if (opType != eOperandType::Register)
|
||||
// {
|
||||
// std::cout << "Invalid operand type; " << line << " (" << opEdit << ") -> Register required\n";
|
||||
// exit(0);
|
||||
// return;
|
||||
// }
|
||||
// m_code.push_back((uint8_t)word);
|
||||
// return;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// std::cout << "Unknown instruction; " << line << " (" << instEdit << ")\n";
|
||||
// exit(0);
|
||||
// }
|
||||
}
|
||||
|
||||
void Assembler::combineDataAndCode(void)
|
||||
|
|
|
|||
|
|
@ -12,8 +12,43 @@ namespace dragon
|
|||
{
|
||||
switch (opCode)
|
||||
{
|
||||
case 0x01: return m_name + "_Test";
|
||||
default: return "UNKNOWN_INST";
|
||||
case OpCodes::wimm_in_dreg_immoffw: return m_name + "_wimm_in_dreg_immoffw";
|
||||
case OpCodes::wimm_in_dreg_regoff: return m_name + "_wimm_in_dreg_regoff";
|
||||
case OpCodes::wimm_in_dreg_immoffb: return m_name + "_wimm_in_dreg_immoffb";
|
||||
case OpCodes::bimm_in_dreg_immoffw: return m_name + "_bimm_in_dreg_immoffw";
|
||||
case OpCodes::bimm_in_dreg_regoff: return m_name + "_bimm_in_dreg_regoff";
|
||||
case OpCodes::bimm_in_dreg_immoffb: return m_name + "_bimm_in_dreg_immoffb";
|
||||
case OpCodes::wdreg_in_dreg_immoffw: return m_name + "_wdreg_in_dreg_immoffw";
|
||||
case OpCodes::wdreg_in_dreg_regoff: return m_name + "_wdreg_in_dreg_regoff";
|
||||
case OpCodes::wdreg_in_dreg_immoffb: return m_name + "_wdreg_in_dreg_immoffb";
|
||||
case OpCodes::bdreg_in_dreg_immoffw: return m_name + "_bdreg_in_dreg_immoffw";
|
||||
case OpCodes::bdreg_in_dreg_regoff: return m_name + "_bdreg_in_dreg_regoff";
|
||||
case OpCodes::bdreg_in_dreg_immoffb: return m_name + "_bdreg_in_dreg_immoffb";
|
||||
case OpCodes::wimm_in_mem_immoffw: return m_name + "_wimm_in_mem_immoffw";
|
||||
case OpCodes::wimm_in_mem_regoff: return m_name + "_wimm_in_mem_regoff";
|
||||
case OpCodes::wimm_in_mem_immoffb: return m_name + "_wimm_in_mem_immoffb";
|
||||
case OpCodes::bimm_in_mem_immoffw: return m_name + "_bimm_in_mem_immoffw";
|
||||
case OpCodes::bimm_in_mem_regoff: return m_name + "_bimm_in_mem_regoff";
|
||||
case OpCodes::bimm_in_mem_immoffb: return m_name + "_bimm_in_mem_immoffb";
|
||||
case OpCodes::wdreg_immoffw_in_dreg: return m_name + "_wdreg_immoffw_in_dreg";
|
||||
case OpCodes::wdreg_regoff_in_dreg: return m_name + "_wdreg_regoff_in_dreg";
|
||||
case OpCodes::wdreg_immoffb_in_dreg: return m_name + "_wdreg_immoffb_in_dreg";
|
||||
case OpCodes::bdreg_immoffw_in_dreg: return m_name + "_bdreg_immoffw_in_dreg";
|
||||
case OpCodes::bdreg_regoff_in_dreg: return m_name + "_bdreg_regoff_in_dreg";
|
||||
case OpCodes::bdreg_immoffb_in_dreg: return m_name + "_bdreg_immoffb_in_dreg";
|
||||
case OpCodes::wmem_immoffw_in_reg: return m_name + "_wmem_immoffw_in_reg";
|
||||
case OpCodes::wmem_regoff_in_reg: return m_name + "_wmem_regoff_in_reg";
|
||||
case OpCodes::wmem_immoffb_in_reg: return m_name + "_wmem_immoffb_in_reg";
|
||||
case OpCodes::bmem_immoffw_in_reg: return m_name + "_bmem_immoffw_in_reg";
|
||||
case OpCodes::bmem_regoff_in_reg: return m_name + "_bmem_regoff_in_reg";
|
||||
case OpCodes::bmem_immoffb_in_reg: return m_name + "_bmem_immoffb_in_reg";
|
||||
case OpCodes::wdreg_immoffw_in_reg: return m_name + "_wdreg_immoffw_in_reg";
|
||||
case OpCodes::wdreg_regoff_in_reg: return m_name + "_wdreg_regoff_in_reg";
|
||||
case OpCodes::wdreg_immoffb_in_reg: return m_name + "_wdreg_immoffb_in_reg";
|
||||
case OpCodes::bdreg_immoffw_in_reg: return m_name + "_bdreg_immoffw_in_reg";
|
||||
case OpCodes::bdreg_regoff_in_reg: return m_name + "_bdreg_regoff_in_reg";
|
||||
case OpCodes::bdreg_immoffb_in_reg: return m_name + "_bdreg_immoffb_in_reg";
|
||||
default: return m_name + "_UNKNOWN_INST";
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -21,19 +56,403 @@ namespace dragon
|
|||
{
|
||||
switch (opCode)
|
||||
{
|
||||
case 0x01: return 2;
|
||||
case OpCodes::wimm_in_dreg_immoffw: return 6;
|
||||
case OpCodes::wimm_in_dreg_regoff: return 5;
|
||||
case OpCodes::wimm_in_dreg_immoffb: return 5;
|
||||
case OpCodes::bimm_in_dreg_immoffw: return 5;
|
||||
case OpCodes::bimm_in_dreg_regoff: return 4;
|
||||
case OpCodes::bimm_in_dreg_immoffb: return 4;
|
||||
case OpCodes::wdreg_in_dreg_immoffw: return 5;
|
||||
case OpCodes::wdreg_in_dreg_regoff: return 4;
|
||||
case OpCodes::wdreg_in_dreg_immoffb: return 4;
|
||||
case OpCodes::bdreg_in_dreg_immoffw: return 5;
|
||||
case OpCodes::bdreg_in_dreg_regoff: return 4;
|
||||
case OpCodes::bdreg_in_dreg_immoffb: return 4;
|
||||
case OpCodes::wimm_in_mem_immoffw: return 7;
|
||||
case OpCodes::wimm_in_mem_regoff: return 6;
|
||||
case OpCodes::wimm_in_mem_immoffb: return 6;
|
||||
case OpCodes::bimm_in_mem_immoffw: return 6;
|
||||
case OpCodes::bimm_in_mem_regoff: return 5;
|
||||
case OpCodes::bimm_in_mem_immoffb: return 5;
|
||||
case OpCodes::wdreg_immoffw_in_dreg: return 5;
|
||||
case OpCodes::wdreg_regoff_in_dreg: return 4;
|
||||
case OpCodes::wdreg_immoffb_in_dreg: return 4;
|
||||
case OpCodes::bdreg_immoffw_in_dreg: return 5;
|
||||
case OpCodes::bdreg_regoff_in_dreg: return 4;
|
||||
case OpCodes::bdreg_immoffb_in_dreg: return 4;
|
||||
case OpCodes::wmem_immoffw_in_reg: return 6;
|
||||
case OpCodes::wmem_regoff_in_reg: return 5;
|
||||
case OpCodes::wmem_immoffb_in_reg: return 5;
|
||||
case OpCodes::bmem_immoffw_in_reg: return 6;
|
||||
case OpCodes::bmem_regoff_in_reg: return 5;
|
||||
case OpCodes::bmem_immoffb_in_reg: return 5;
|
||||
case OpCodes::wdreg_immoffw_in_reg: return 5;
|
||||
case OpCodes::wdreg_regoff_in_reg: return 4;
|
||||
case OpCodes::wdreg_immoffb_in_reg: return 4;
|
||||
case OpCodes::bdreg_immoffw_in_reg: return 5;
|
||||
case OpCodes::bdreg_regoff_in_reg: return 4;
|
||||
case OpCodes::bdreg_immoffb_in_reg: return 4;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
bool ExtMov::execute(VirtualCPU& vcpu)
|
||||
{
|
||||
auto& mem = DragonRuntime::memMap;
|
||||
uint8_t inst = vcpu.fetch8();
|
||||
switch (inst)
|
||||
{
|
||||
case 0x01:
|
||||
case OpCodes::wimm_in_dreg_immoffw:
|
||||
{
|
||||
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wimm_in_dreg_regoff:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wimm_in_dreg_immoffb:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_dreg_immoffw:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_dreg_regoff:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_dreg_immoffb:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_in_dreg_immoffw:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, mem.read16(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_in_dreg_regoff:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, mem.read16(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_in_dreg_immoffb:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write16(dest_mem + offset, mem.read16(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_in_dreg_immoffw:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, mem.read8(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_in_dreg_regoff:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, mem.read8(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_in_dreg_immoffb:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
int16_t src_mem = vcpu.readRegister(vcpu.fetch8());
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
mem.write8(dest_mem + offset, mem.read8(src_mem));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wimm_in_mem_immoffw:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wimm_in_mem_regoff:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wimm_in_mem_immoffb:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int16_t src_wimm = vcpu.fetch16();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
mem.write16(dest_mem + offset, src_wimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_mem_immoffw:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_mem_regoff:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::bimm_in_mem_immoffb:
|
||||
{
|
||||
uint16_t dest_mem = vcpu.fetch16();
|
||||
int8_t src_bimm = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
mem.write8(dest_mem + offset, src_bimm);
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_immoffw_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write16(dest_mem, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_regoff_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write16(dest_mem, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_immoffb_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write16(dest_mem, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_immoffw_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write8(dest_mem, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_regoff_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write8(dest_mem, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_immoffb_in_dreg:
|
||||
{
|
||||
uint8_t dest_dreg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t dest_mem = vcpu.readRegister(dest_dreg);
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
mem.write8(dest_mem, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wmem_immoffw_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wmem_regoff_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wmem_immoffb_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bmem_immoffw_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bmem_regoff_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bmem_immoffb_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint16_t src_mem = vcpu.fetch16();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_immoffw_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_regoff_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::wdreg_immoffb_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister16(dest_reg, mem.read16(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_immoffw_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.fetch16();
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_regoff_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint16_t offset = vcpu.readRegister(vcpu.fetch8());
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
case OpCodes::bdreg_immoffb_in_reg:
|
||||
{
|
||||
uint8_t dest_reg = vcpu.fetch8();
|
||||
uint8_t src_dreg = vcpu.fetch8();
|
||||
uint8_t offset = vcpu.fetch8();
|
||||
|
||||
uint16_t src_mem = vcpu.readRegister(src_dreg);
|
||||
vcpu.writeRegister8(dest_reg, mem.read8(src_mem + offset));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -10,6 +10,49 @@ namespace dragon
|
|||
{
|
||||
class ExtMov : public data::CPUExtension
|
||||
{
|
||||
public: class OpCodes
|
||||
{
|
||||
public:
|
||||
inline static constexpr uint8_t wimm_in_dreg_immoffw = 0x10;
|
||||
inline static constexpr uint8_t wimm_in_dreg_regoff = 0x11;
|
||||
inline static constexpr uint8_t wimm_in_dreg_immoffb = 0x12;
|
||||
inline static constexpr uint8_t bimm_in_dreg_immoffw = 0x13;
|
||||
inline static constexpr uint8_t bimm_in_dreg_regoff = 0x14;
|
||||
inline static constexpr uint8_t bimm_in_dreg_immoffb = 0x15;
|
||||
inline static constexpr uint8_t wdreg_in_dreg_immoffw = 0x16;
|
||||
inline static constexpr uint8_t wdreg_in_dreg_regoff = 0x17;
|
||||
inline static constexpr uint8_t wdreg_in_dreg_immoffb = 0x18;
|
||||
inline static constexpr uint8_t bdreg_in_dreg_immoffw = 0x19;
|
||||
inline static constexpr uint8_t bdreg_in_dreg_regoff = 0x1A;
|
||||
inline static constexpr uint8_t bdreg_in_dreg_immoffb = 0x1B;
|
||||
|
||||
inline static constexpr uint8_t wimm_in_mem_immoffw = 0x30;
|
||||
inline static constexpr uint8_t wimm_in_mem_regoff = 0x31;
|
||||
inline static constexpr uint8_t wimm_in_mem_immoffb = 0x32;
|
||||
inline static constexpr uint8_t bimm_in_mem_immoffw = 0x33;
|
||||
inline static constexpr uint8_t bimm_in_mem_regoff = 0x34;
|
||||
inline static constexpr uint8_t bimm_in_mem_immoffb = 0x35;
|
||||
|
||||
inline static constexpr uint8_t wdreg_immoffw_in_dreg = 0x40;
|
||||
inline static constexpr uint8_t wdreg_regoff_in_dreg = 0x41;
|
||||
inline static constexpr uint8_t wdreg_immoffb_in_dreg = 0x42;
|
||||
inline static constexpr uint8_t bdreg_immoffw_in_dreg = 0x43;
|
||||
inline static constexpr uint8_t bdreg_regoff_in_dreg = 0x44;
|
||||
inline static constexpr uint8_t bdreg_immoffb_in_dreg = 0x45;
|
||||
|
||||
inline static constexpr uint8_t wmem_immoffw_in_reg = 0x50;
|
||||
inline static constexpr uint8_t wmem_regoff_in_reg = 0x51;
|
||||
inline static constexpr uint8_t wmem_immoffb_in_reg = 0x52;
|
||||
inline static constexpr uint8_t bmem_immoffw_in_reg = 0x53;
|
||||
inline static constexpr uint8_t bmem_regoff_in_reg = 0x54;
|
||||
inline static constexpr uint8_t bmem_immoffb_in_reg = 0x55;
|
||||
inline static constexpr uint8_t wdreg_immoffw_in_reg = 0x56;
|
||||
inline static constexpr uint8_t wdreg_regoff_in_reg = 0x57;
|
||||
inline static constexpr uint8_t wdreg_immoffb_in_reg = 0x58;
|
||||
inline static constexpr uint8_t bdreg_immoffw_in_reg = 0x59;
|
||||
inline static constexpr uint8_t bdreg_regoff_in_reg = 0x5A;
|
||||
inline static constexpr uint8_t bdreg_immoffb_in_reg = 0x5B;
|
||||
};
|
||||
public:
|
||||
inline ExtMov(void) : data::CPUExtension(data::OpCodes::Ext01, "extmov") { }
|
||||
ostd::String getOpCodeString(uint8_t opCode) override;
|
||||
|
|
|
|||
|
|
@ -13,8 +13,8 @@ namespace dragon
|
|||
{
|
||||
VirtualCPU::VirtualCPU(IMemoryDevice& memory) : m_memory(memory)
|
||||
{
|
||||
writeRegister(data::Registers::SP, (uint16_t)(0xFFFF - 1));
|
||||
writeRegister(data::Registers::FP, (uint16_t)(0xFFFF - 1));
|
||||
writeRegister16(data::Registers::SP, (uint16_t)(0xFFFF - 1));
|
||||
writeRegister16(data::Registers::FP, (uint16_t)(0xFFFF - 1));
|
||||
|
||||
for (int32_t i = 0; i < 16; i++)
|
||||
m_extensions[i] = nullptr;
|
||||
|
|
@ -26,19 +26,26 @@ namespace dragon
|
|||
return m_registers[reg];
|
||||
}
|
||||
|
||||
int16_t VirtualCPU::writeRegister(uint8_t reg, int16_t value)
|
||||
int16_t VirtualCPU::writeRegister16(uint8_t reg, int16_t value)
|
||||
{
|
||||
if (reg >= data::Registers::Last) return 0x0000; //TODO: Error
|
||||
m_registers[reg] = value;
|
||||
return value;
|
||||
}
|
||||
|
||||
int8_t VirtualCPU::writeRegister8(uint8_t reg, int8_t value)
|
||||
{
|
||||
if (reg >= data::Registers::Last) return 0x0000; //TODO: Error
|
||||
m_registers[reg] = value & 0x00FF;
|
||||
return value;
|
||||
}
|
||||
|
||||
int8_t VirtualCPU::fetch8(void)
|
||||
{
|
||||
uint16_t nextInstAddr = readRegister(data::Registers::IP);
|
||||
m_currentAddr = nextInstAddr;
|
||||
int8_t inst = m_memory.read8(nextInstAddr);
|
||||
writeRegister(data::Registers::IP, nextInstAddr + 1);
|
||||
writeRegister16(data::Registers::IP, nextInstAddr + 1);
|
||||
return inst;
|
||||
}
|
||||
|
||||
|
|
@ -47,7 +54,7 @@ namespace dragon
|
|||
uint16_t nextInstAddr = readRegister(data::Registers::IP);
|
||||
m_currentAddr = nextInstAddr;
|
||||
int16_t inst = m_memory.read16(nextInstAddr);
|
||||
writeRegister(data::Registers::IP, nextInstAddr + 2);
|
||||
writeRegister16(data::Registers::IP, nextInstAddr + 2);
|
||||
return inst;
|
||||
}
|
||||
|
||||
|
|
@ -55,14 +62,14 @@ namespace dragon
|
|||
{
|
||||
uint16_t stackAddr = readRegister(data::Registers::SP);
|
||||
m_memory.write16(stackAddr, value);
|
||||
writeRegister(data::Registers::SP, stackAddr - 2);
|
||||
writeRegister16(data::Registers::SP, stackAddr - 2);
|
||||
m_stackFrameSize += 2;
|
||||
}
|
||||
|
||||
int16_t VirtualCPU::popFromStack(void)
|
||||
{
|
||||
uint16_t nextSP = readRegister(data::Registers::SP) + 2;
|
||||
writeRegister(data::Registers::SP, nextSP);
|
||||
writeRegister16(data::Registers::SP, nextSP);
|
||||
int16_t value = m_memory.read16(nextSP);
|
||||
m_stackFrameSize -= 2;
|
||||
return value;
|
||||
|
|
@ -98,32 +105,32 @@ namespace dragon
|
|||
pushToStack(readRegister(data::Registers::FP));
|
||||
pushToStack(m_stackFrameSize);
|
||||
|
||||
writeRegister(data::Registers::PP, argStartAddr);
|
||||
writeRegister(data::Registers::FP, readRegister(data::Registers::SP));
|
||||
writeRegister16(data::Registers::PP, argStartAddr);
|
||||
writeRegister16(data::Registers::FP, readRegister(data::Registers::SP));
|
||||
m_stackFrameSize = 0;
|
||||
}
|
||||
|
||||
void VirtualCPU::popStackFrame(void)
|
||||
{
|
||||
uint16_t framePointerAddr = readRegister(data::Registers::FP);
|
||||
writeRegister(data::Registers::SP, framePointerAddr);
|
||||
writeRegister16(data::Registers::SP, framePointerAddr);
|
||||
m_stackFrameSize = popFromStack();
|
||||
// uint16_t tmpStackFrameSize = m_stackFrameSize;
|
||||
|
||||
writeRegister(data::Registers::FP, popFromStack());
|
||||
writeRegister(data::Registers::IP, popFromStack());
|
||||
writeRegister(data::Registers::ACC, popFromStack());
|
||||
writeRegister(data::Registers::PP, popFromStack());
|
||||
writeRegister(data::Registers::R10, popFromStack());
|
||||
writeRegister(data::Registers::R9, popFromStack());
|
||||
writeRegister(data::Registers::R8, popFromStack());
|
||||
writeRegister(data::Registers::R7, popFromStack());
|
||||
writeRegister(data::Registers::R6, popFromStack());
|
||||
writeRegister(data::Registers::R5, popFromStack());
|
||||
writeRegister(data::Registers::R4, popFromStack());
|
||||
writeRegister(data::Registers::R3, popFromStack());
|
||||
writeRegister(data::Registers::R2, popFromStack());
|
||||
writeRegister(data::Registers::R1, popFromStack());
|
||||
writeRegister16(data::Registers::FP, popFromStack());
|
||||
writeRegister16(data::Registers::IP, popFromStack());
|
||||
writeRegister16(data::Registers::ACC, popFromStack());
|
||||
writeRegister16(data::Registers::PP, popFromStack());
|
||||
writeRegister16(data::Registers::R10, popFromStack());
|
||||
writeRegister16(data::Registers::R9, popFromStack());
|
||||
writeRegister16(data::Registers::R8, popFromStack());
|
||||
writeRegister16(data::Registers::R7, popFromStack());
|
||||
writeRegister16(data::Registers::R6, popFromStack());
|
||||
writeRegister16(data::Registers::R5, popFromStack());
|
||||
writeRegister16(data::Registers::R4, popFromStack());
|
||||
writeRegister16(data::Registers::R3, popFromStack());
|
||||
writeRegister16(data::Registers::R2, popFromStack());
|
||||
writeRegister16(data::Registers::R1, popFromStack());
|
||||
|
||||
uint16_t nArgs = popFromStack();
|
||||
for (int32_t i = 0; i < nArgs; i++)
|
||||
|
|
@ -147,7 +154,7 @@ namespace dragon
|
|||
if (flg >= 16) return;
|
||||
m_tempFlags.value = readRegister(data::Registers::FL);
|
||||
ostd::Bits::val(m_tempFlags, flg, val);
|
||||
writeRegister(data::Registers::FL, m_tempFlags.value);
|
||||
writeRegister16(data::Registers::FL, m_tempFlags.value);
|
||||
}
|
||||
|
||||
void VirtualCPU::handleInterrupt(uint8_t intValue, bool hardware)
|
||||
|
|
@ -160,7 +167,7 @@ namespace dragon
|
|||
pushStackFrame();
|
||||
m_subroutineCounter++;
|
||||
m_interruptHandlerCount++;
|
||||
writeRegister(data::Registers::IP, handlerAddress);
|
||||
writeRegister16(data::Registers::IP, handlerAddress);
|
||||
if (m_debugModeEnabled && hardware)
|
||||
{
|
||||
DragonRuntime::tCallInfo interruptData;
|
||||
|
|
@ -225,7 +232,7 @@ namespace dragon
|
|||
{
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t literal = fetch16();
|
||||
writeRegister(regAddr, literal);
|
||||
writeRegister16(regAddr, literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovImmMem:
|
||||
|
|
@ -240,7 +247,7 @@ namespace dragon
|
|||
uint8_t destRegAddr = fetch8();
|
||||
uint8_t srcRegAddr = fetch8();
|
||||
int16_t value = readRegister(srcRegAddr);
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister16(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovRegMem:
|
||||
|
|
@ -256,7 +263,7 @@ namespace dragon
|
|||
uint8_t destRegAddr = fetch8();
|
||||
uint16_t addr = fetch16();
|
||||
int16_t value = m_memory.read16(addr);
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister16(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovDerefRegReg:
|
||||
|
|
@ -265,7 +272,7 @@ namespace dragon
|
|||
uint8_t srcRegAddr = fetch8();
|
||||
uint16_t addr = readRegister(srcRegAddr);
|
||||
int16_t value = m_memory.read16(addr);
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister16(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovDerefRegMem:
|
||||
|
|
@ -277,16 +284,16 @@ namespace dragon
|
|||
m_memory.write16(destAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovImmRegOffReg:
|
||||
{
|
||||
uint8_t destRegAddr = fetch8();
|
||||
uint16_t addr = fetch16();
|
||||
uint8_t offRegAddr = fetch8();
|
||||
int16_t offset = readRegister(offRegAddr);
|
||||
int16_t value = m_memory.read16(addr + offset);
|
||||
writeRegister(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
// case data::OpCodes::MovImmRegOffReg:
|
||||
// {
|
||||
// uint8_t destRegAddr = fetch8();
|
||||
// uint16_t addr = fetch16();
|
||||
// uint8_t offRegAddr = fetch8();
|
||||
// int16_t offset = readRegister(offRegAddr);
|
||||
// int16_t value = m_memory.read16(addr + offset);
|
||||
// writeRegister(destRegAddr, value);
|
||||
// }
|
||||
// break;
|
||||
case data::OpCodes::MovRegDerefReg:
|
||||
{
|
||||
uint8_t destRegAddr = fetch8();
|
||||
|
|
@ -380,14 +387,14 @@ namespace dragon
|
|||
uint8_t destRegAddr = fetch8();
|
||||
uint16_t srcAddr = fetch16();
|
||||
int8_t value = m_memory.read8(srcAddr);
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister8(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovByteImmReg:
|
||||
{
|
||||
uint8_t destRegAddr = fetch8();
|
||||
int8_t value = fetch8();
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister8(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovByteDerefRegReg:
|
||||
|
|
@ -396,7 +403,7 @@ namespace dragon
|
|||
uint8_t srcRegAddr = fetch8();
|
||||
uint16_t srcAddr = readRegister(srcRegAddr);
|
||||
int8_t value = m_memory.read8(srcAddr);
|
||||
writeRegister(destRegAddr, value);
|
||||
writeRegister8(destRegAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MovByteRegMem:
|
||||
|
|
@ -412,7 +419,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t literal = fetch16();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, regValue + literal);
|
||||
writeRegister16(data::Registers::ACC, regValue + literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::AddRegReg:
|
||||
|
|
@ -421,7 +428,7 @@ namespace dragon
|
|||
uint8_t regAddr2 = fetch8();
|
||||
int16_t regValue1 = readRegister(regAddr1);
|
||||
int16_t regValue2 = readRegister(regAddr2);
|
||||
writeRegister(data::Registers::ACC, regValue1 + regValue2);
|
||||
writeRegister16(data::Registers::ACC, regValue1 + regValue2);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::SubImmReg:
|
||||
|
|
@ -429,7 +436,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t literal = fetch16();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, regValue - literal);
|
||||
writeRegister16(data::Registers::ACC, regValue - literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::SubRegReg:
|
||||
|
|
@ -438,7 +445,7 @@ namespace dragon
|
|||
uint8_t regAddr2 = fetch8();
|
||||
int16_t regValue1 = readRegister(regAddr1);
|
||||
int16_t regValue2 = readRegister(regAddr2);
|
||||
writeRegister(data::Registers::ACC, regValue1 - regValue2);
|
||||
writeRegister16(data::Registers::ACC, regValue1 - regValue2);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MulImmReg:
|
||||
|
|
@ -446,7 +453,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t literal = fetch16();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, regValue * literal);
|
||||
writeRegister16(data::Registers::ACC, regValue * literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::MulRegReg:
|
||||
|
|
@ -455,7 +462,7 @@ namespace dragon
|
|||
uint8_t regAddr2 = fetch8();
|
||||
int16_t regValue1 = readRegister(regAddr1);
|
||||
int16_t regValue2 = readRegister(regAddr2);
|
||||
writeRegister(data::Registers::ACC, regValue1 * regValue2);
|
||||
writeRegister16(data::Registers::ACC, regValue1 * regValue2);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::DivImmReg: //TODO: Division by zero is unhandled
|
||||
|
|
@ -465,8 +472,8 @@ namespace dragon
|
|||
int16_t regValue = readRegister(regAddr);
|
||||
int16_t quotient = regValue / literal;
|
||||
int16_t reminder = regValue % literal;
|
||||
writeRegister(data::Registers::ACC, quotient);
|
||||
writeRegister(data::Registers::RV, reminder);
|
||||
writeRegister16(data::Registers::ACC, quotient);
|
||||
writeRegister16(data::Registers::RV, reminder);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::DivRegReg: //TODO: Division by zero is unhandled
|
||||
|
|
@ -477,22 +484,22 @@ namespace dragon
|
|||
int16_t regValue2 = readRegister(regAddr2);
|
||||
int16_t quotient = regValue1 / regValue2;
|
||||
int16_t reminder = regValue1 % regValue2;
|
||||
writeRegister(data::Registers::ACC, quotient);
|
||||
writeRegister(data::Registers::RV, reminder);
|
||||
writeRegister16(data::Registers::ACC, quotient);
|
||||
writeRegister16(data::Registers::RV, reminder);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::IncReg:
|
||||
{
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
writeRegister(regAddr, regValue + 1);
|
||||
writeRegister16(regAddr, regValue + 1);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::DecReg:
|
||||
{
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
writeRegister(regAddr, regValue - 1);
|
||||
writeRegister16(regAddr, regValue - 1);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::RShiftRegImm:
|
||||
|
|
@ -501,7 +508,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
regValue = regValue >> literal;
|
||||
writeRegister(regAddr, regValue);
|
||||
writeRegister16(regAddr, regValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::RShiftRegReg:
|
||||
|
|
@ -511,7 +518,7 @@ namespace dragon
|
|||
int16_t shiftValue = readRegister(shiftRegAddr);
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
regValue = regValue >> shiftValue;
|
||||
writeRegister(regAddr, regValue);
|
||||
writeRegister16(regAddr, regValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::LShiftRegImm:
|
||||
|
|
@ -520,7 +527,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
regValue = regValue << literal;
|
||||
writeRegister(regAddr, regValue);
|
||||
writeRegister16(regAddr, regValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::LShiftRegReg:
|
||||
|
|
@ -530,7 +537,7 @@ namespace dragon
|
|||
int16_t shiftValue = readRegister(shiftRegAddr);
|
||||
int16_t regValue = readRegister(regAddr);
|
||||
regValue = regValue << shiftValue;
|
||||
writeRegister(regAddr, regValue);
|
||||
writeRegister16(regAddr, regValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::AndRegImm:
|
||||
|
|
@ -538,7 +545,7 @@ namespace dragon
|
|||
int16_t literal = fetch16();
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, value & literal);
|
||||
writeRegister16(data::Registers::ACC, value & literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::AndRegReg:
|
||||
|
|
@ -547,7 +554,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
int16_t andValue = readRegister(andRegAddr);
|
||||
writeRegister(data::Registers::ACC, value & andValue);
|
||||
writeRegister16(data::Registers::ACC, value & andValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::OrRegImm:
|
||||
|
|
@ -555,7 +562,7 @@ namespace dragon
|
|||
int16_t literal = fetch16();
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, value | literal);
|
||||
writeRegister16(data::Registers::ACC, value | literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::OrRegReg:
|
||||
|
|
@ -564,7 +571,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
int16_t andValue = readRegister(andRegAddr);
|
||||
writeRegister(data::Registers::ACC, value | andValue);
|
||||
writeRegister16(data::Registers::ACC, value | andValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::XorRegImm:
|
||||
|
|
@ -572,7 +579,7 @@ namespace dragon
|
|||
int16_t literal = fetch16();
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, value ^ literal);
|
||||
writeRegister16(data::Registers::ACC, value ^ literal);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::XorRegReg:
|
||||
|
|
@ -581,14 +588,14 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
int16_t andValue = readRegister(andRegAddr);
|
||||
writeRegister(data::Registers::ACC, value ^ andValue);
|
||||
writeRegister16(data::Registers::ACC, value ^ andValue);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::NotReg:
|
||||
{
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
writeRegister(data::Registers::ACC, ~value);
|
||||
writeRegister16(data::Registers::ACC, ~value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::NegReg:
|
||||
|
|
@ -596,7 +603,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int16_t value = readRegister(regAddr);
|
||||
value *= -1;
|
||||
writeRegister(regAddr, value);
|
||||
writeRegister16(regAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::NegByteReg:
|
||||
|
|
@ -604,7 +611,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
int8_t value = (int8_t)readRegister(regAddr);
|
||||
value *= -1;
|
||||
writeRegister(regAddr, (int16_t)(0x00FF & value));
|
||||
writeRegister8(regAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpNotEqImm:
|
||||
|
|
@ -613,7 +620,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value != accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpNotEqReg:
|
||||
|
|
@ -623,7 +630,7 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value != accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpEqImm:
|
||||
|
|
@ -632,7 +639,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value == accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpEqReg:
|
||||
|
|
@ -642,7 +649,7 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value == accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpGrImm:
|
||||
|
|
@ -651,7 +658,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value > accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpGrReg:
|
||||
|
|
@ -661,7 +668,7 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value > accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpLessImm:
|
||||
|
|
@ -670,7 +677,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value < accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpLessReg:
|
||||
|
|
@ -680,7 +687,7 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value < accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpGeImm:
|
||||
|
|
@ -689,7 +696,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value >= accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpGeReg:
|
||||
|
|
@ -699,7 +706,7 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value >= accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpLeImm:
|
||||
|
|
@ -708,7 +715,7 @@ namespace dragon
|
|||
int16_t value = fetch16();
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value <= accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::JmpLeReg:
|
||||
|
|
@ -718,13 +725,13 @@ namespace dragon
|
|||
int16_t value = readRegister(regAddr);
|
||||
int16_t accValue = readRegister(data::Registers::ACC);
|
||||
if (value <= accValue)
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::Jmp:
|
||||
{
|
||||
uint16_t addr = fetch16();
|
||||
writeRegister(data::Registers::IP, addr);
|
||||
writeRegister16(data::Registers::IP, addr);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::Halt:
|
||||
|
|
@ -750,14 +757,14 @@ namespace dragon
|
|||
{
|
||||
uint8_t regAddr = fetch8();
|
||||
int16_t value = popFromStack();
|
||||
writeRegister(regAddr, value);
|
||||
writeRegister16(regAddr, value);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::CallImm:
|
||||
{
|
||||
uint16_t subroutineAddr = fetch16();
|
||||
pushStackFrame();
|
||||
writeRegister(data::Registers::IP, subroutineAddr);
|
||||
writeRegister16(data::Registers::IP, subroutineAddr);
|
||||
m_subroutineCounter++;
|
||||
}
|
||||
break;
|
||||
|
|
@ -766,7 +773,7 @@ namespace dragon
|
|||
uint8_t regAddr = fetch8();
|
||||
uint16_t subroutineAddr = readRegister(regAddr);
|
||||
pushStackFrame();
|
||||
writeRegister(data::Registers::IP, subroutineAddr);
|
||||
writeRegister16(data::Registers::IP, subroutineAddr);
|
||||
m_subroutineCounter++;
|
||||
}
|
||||
break;
|
||||
|
|
@ -783,8 +790,8 @@ namespace dragon
|
|||
if (!isInSubRoutine()) break;
|
||||
int16_t pp_val = readRegister(data::Registers::PP);
|
||||
int16_t arg_data = m_memory.read16(pp_val);
|
||||
writeRegister(data::Registers::PP, pp_val - 2);
|
||||
writeRegister(regAddr, arg_data);
|
||||
writeRegister16(data::Registers::PP, pp_val - 2);
|
||||
writeRegister16(regAddr, arg_data);
|
||||
}
|
||||
break;
|
||||
case data::OpCodes::RetInt:
|
||||
|
|
@ -884,8 +891,8 @@ namespace dragon
|
|||
pushToStack(m_stackFrameSize);
|
||||
stackFrameString.add("StackFrame: ").add(m_stackFrameSize).add(", ");
|
||||
|
||||
writeRegister(data::Registers::PP, argStartAddr);
|
||||
writeRegister(data::Registers::FP, readRegister(data::Registers::SP));
|
||||
writeRegister16(data::Registers::PP, argStartAddr);
|
||||
writeRegister16(data::Registers::FP, readRegister(data::Registers::SP));
|
||||
stackFrameString.add("New FP: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::FP), true, 2));
|
||||
m_stackFrameSize = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,9 @@ namespace dragon
|
|||
public:
|
||||
VirtualCPU(IMemoryDevice& memory);
|
||||
int16_t readRegister(uint8_t reg);
|
||||
int16_t writeRegister(uint8_t reg, int16_t value);
|
||||
int16_t writeRegister16(uint8_t reg, int16_t value);
|
||||
int8_t writeRegister8(uint8_t reg, int8_t value);
|
||||
//TODO: Implement writeRegister8 and writeRegister16 functions (maybe for readRegister aswell)
|
||||
|
||||
int8_t fetch8(void);
|
||||
int16_t fetch16(void);
|
||||
|
|
|
|||
|
|
@ -306,7 +306,7 @@ namespace dragon
|
|||
uint16_t reset_ip_addr = 0x0000;
|
||||
if (verbose)
|
||||
out.fg(ostd::ConsoleColors::BrightYellow).p(" Reset IP register: ").p(ostd::Utils::getHexStr(reset_ip_addr, true, 2).cpp_str()).nl();
|
||||
cpu.writeRegister(dragon::data::Registers::IP, reset_ip_addr);
|
||||
cpu.writeRegister16(dragon::data::Registers::IP, reset_ip_addr);
|
||||
|
||||
if (verbose)
|
||||
out.fg(ostd::ConsoleColors::BrightYellow).p(" Debug mode enabled: ").p(STR_BOOL(debugModeEnabled)).nl();
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ namespace dragon
|
|||
case data::OpCodes::MovMemReg: return "MovMemReg";
|
||||
case data::OpCodes::MovDerefRegReg: return "MovDerefRegReg";
|
||||
case data::OpCodes::MovDerefRegMem: return "MovDerefRegMem";
|
||||
case data::OpCodes::MovImmRegOffReg: return "MovImmRegOffReg";
|
||||
// case data::OpCodes::MovImmRegOffReg: return "MovImmRegOffReg";
|
||||
case data::OpCodes::MovRegDerefReg: return "MovRegDerefReg";
|
||||
case data::OpCodes::MovMemDerefReg: return "MovMemDerefReg";
|
||||
case data::OpCodes::MovImmDerefReg: return "MovImmDerefReg";
|
||||
|
|
@ -107,7 +107,7 @@ namespace dragon
|
|||
{
|
||||
CPUExtension* ext = DragonRuntime::cpu.getCurrentCPUExtension();
|
||||
if (ext != nullptr)
|
||||
return ext->getInstructionSIze(DragonRuntime::cpu.getCurrentCPUExtensionInstruction());
|
||||
return 1 + ext->getInstructionSIze(DragonRuntime::cpu.getCurrentCPUExtensionInstruction());
|
||||
switch (opCode)
|
||||
{
|
||||
case data::OpCodes::NoOp: return 1;
|
||||
|
|
@ -120,7 +120,7 @@ namespace dragon
|
|||
case data::OpCodes::MovMemReg: return 4;
|
||||
case data::OpCodes::MovDerefRegReg: return 3;
|
||||
case data::OpCodes::MovDerefRegMem: return 4;
|
||||
case data::OpCodes::MovImmRegOffReg: return 5;
|
||||
// case data::OpCodes::MovImmRegOffReg: return 5;
|
||||
case data::OpCodes::MovRegDerefReg: return 3;
|
||||
case data::OpCodes::MovMemDerefReg: return 4;
|
||||
case data::OpCodes::MovImmDerefReg: return 4;
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ namespace dragon
|
|||
inline static constexpr uint8_t MovMemReg = 0x13;
|
||||
inline static constexpr uint8_t MovImmMem = 0x14;
|
||||
inline static constexpr uint8_t MovDerefRegReg = 0x15;
|
||||
inline static constexpr uint8_t MovImmRegOffReg = 0x16;
|
||||
// inline static constexpr uint8_t MovImmRegOffReg = 0x16;
|
||||
inline static constexpr uint8_t MovDerefRegMem = 0x17;
|
||||
inline static constexpr uint8_t MovRegDerefReg = 0x18;
|
||||
inline static constexpr uint8_t MovMemDerefReg = 0x19;
|
||||
|
|
|
|||
Loading…
Reference in a new issue