789 lines
No EOL
24 KiB
C++
789 lines
No EOL
24 KiB
C++
#include "VirtualCPU.hpp"
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#include "../tools/GlobalData.hpp"
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#include <ostd/Defines.hpp>
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#include <ostd/Utils.hpp>
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#include <iostream>
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namespace dragon
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{
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namespace hw
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{
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VirtualCPU::VirtualCPU(IMemoryDevice& memory) : m_memory(memory)
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{
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writeRegister(data::Registers::SP, (uint16_t)(0xFFFF - 1));
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writeRegister(data::Registers::FP, (uint16_t)(0xFFFF - 1));
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}
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int16_t VirtualCPU::readRegister(uint8_t reg)
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{
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if (reg >= data::Registers::Last) return 0x0000; //TODO: Error
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return m_registers[reg];
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}
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int16_t VirtualCPU::writeRegister(uint8_t reg, int16_t value)
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{
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if (reg >= data::Registers::Last) return 0x0000; //TODO: Error
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m_registers[reg] = value;
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return value;
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}
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int8_t VirtualCPU::fetch8(void)
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{
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uint16_t nextInstAddr = readRegister(data::Registers::IP);
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int8_t inst = m_memory.read8(nextInstAddr);
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writeRegister(data::Registers::IP, nextInstAddr + 1);
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return inst;
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}
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int16_t VirtualCPU::fetch16(void)
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{
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uint16_t nextInstAddr = readRegister(data::Registers::IP);
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int16_t inst = m_memory.read16(nextInstAddr);
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writeRegister(data::Registers::IP, nextInstAddr + 2);
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return inst;
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}
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void VirtualCPU::pushToStack(int16_t value)
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{
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uint16_t stackAddr = readRegister(data::Registers::SP);
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m_memory.write16(stackAddr, value);
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writeRegister(data::Registers::SP, stackAddr - 2);
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m_stackFrameSize += 2;
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}
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int16_t VirtualCPU::popFromStack(void)
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{
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uint16_t nextSP = readRegister(data::Registers::SP) + 2;
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writeRegister(data::Registers::SP, nextSP);
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int16_t value = m_memory.read16(nextSP);
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m_stackFrameSize -= 2;
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return value;
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}
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void VirtualCPU::pushStackFrame(void)
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{
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if (m_debugModeEnabled)
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{
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__debug_store_stack_frame_string_on_push();
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return;
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}
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uint16_t argStartAddr = readRegister(data::Registers::SP) + 2;
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uint16_t argCount = m_memory.read16(argStartAddr);
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if (argCount == 0)
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argStartAddr = 0;
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else
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argStartAddr += (argCount * 2);
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pushToStack(readRegister(data::Registers::R1));
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pushToStack(readRegister(data::Registers::R2));
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pushToStack(readRegister(data::Registers::R3));
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pushToStack(readRegister(data::Registers::R4));
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pushToStack(readRegister(data::Registers::R5));
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pushToStack(readRegister(data::Registers::R6));
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pushToStack(readRegister(data::Registers::R7));
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pushToStack(readRegister(data::Registers::R8));
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pushToStack(readRegister(data::Registers::R9));
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pushToStack(readRegister(data::Registers::R10));
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pushToStack(readRegister(data::Registers::PP));
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pushToStack(readRegister(data::Registers::ACC));
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pushToStack(readRegister(data::Registers::IP));
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pushToStack(readRegister(data::Registers::FP));
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pushToStack(m_stackFrameSize);
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writeRegister(data::Registers::PP, argStartAddr);
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writeRegister(data::Registers::FP, readRegister(data::Registers::SP));
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m_stackFrameSize = 0;
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}
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void VirtualCPU::popStackFrame(void)
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{
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uint16_t framePointerAddr = readRegister(data::Registers::FP);
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writeRegister(data::Registers::SP, framePointerAddr);
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m_stackFrameSize = popFromStack();
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// uint16_t tmpStackFrameSize = m_stackFrameSize;
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writeRegister(data::Registers::FP, popFromStack());
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writeRegister(data::Registers::IP, popFromStack());
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writeRegister(data::Registers::ACC, popFromStack());
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writeRegister(data::Registers::PP, popFromStack());
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writeRegister(data::Registers::R10, popFromStack());
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writeRegister(data::Registers::R9, popFromStack());
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writeRegister(data::Registers::R8, popFromStack());
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writeRegister(data::Registers::R7, popFromStack());
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writeRegister(data::Registers::R6, popFromStack());
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writeRegister(data::Registers::R5, popFromStack());
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writeRegister(data::Registers::R4, popFromStack());
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writeRegister(data::Registers::R3, popFromStack());
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writeRegister(data::Registers::R2, popFromStack());
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writeRegister(data::Registers::R1, popFromStack());
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uint16_t nArgs = popFromStack();
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for (int32_t i = 0; i < nArgs; i++)
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{
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popFromStack();
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// writeRegister(data::Registers::FP, readRegister(data::Registers::FP) - 2);
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}
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// writeRegister(data::Registers::FP, framePointerAddr + tmpStackFrameSize);
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}
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bool VirtualCPU::readFlag(uint8_t flg)
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{
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if (flg >= 16) return false;
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m_tempFlags.value = readRegister(data::Registers::FL);
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return ostd::Bits::get(m_tempFlags, flg);
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}
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void VirtualCPU::setFlag(uint8_t flg, bool val)
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{
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if (flg >= 16) return;
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m_tempFlags.value = readRegister(data::Registers::FL);
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ostd::Bits::val(m_tempFlags, flg, val);
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writeRegister(data::Registers::FL, m_tempFlags.value);
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}
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void VirtualCPU::handleInterrupt(uint8_t intValue)
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{
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uint16_t entryPointer = data::MemoryMapAddresses::IntVector_Start + (intValue * 3);
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uint8_t interruptStatus = m_memory.read8(entryPointer);
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if (interruptStatus != 0xFF) return;
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uint16_t handlerAddress = m_memory.read16(entryPointer + 1);
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if (!m_isInInterruptHandler)
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{
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pushToStack(0);
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pushStackFrame();
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}
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m_isInInterruptHandler = true;
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writeRegister(data::Registers::IP, handlerAddress);
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}
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bool VirtualCPU::execute(void)
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{
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if (m_halt) return false;
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m_isDebugBreakPoint = false;
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uint8_t inst = fetch8();
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m_currentInst = inst;
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switch (inst)
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{
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case data::OpCodes::NoOp:
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{
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}
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break;
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case data::OpCodes::DEBUG_Break:
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{
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m_isDebugBreakPoint = true;
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}
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break;
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case data::OpCodes::MovImmReg:
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{
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uint8_t regAddr = fetch8();
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int16_t literal = fetch16();
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writeRegister(regAddr, literal);
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}
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break;
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case data::OpCodes::MovImmMem:
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{
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uint16_t addr = fetch16();
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int16_t literal = fetch16();
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m_memory.write16(addr, literal);
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}
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break;
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case data::OpCodes::MovRegReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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int16_t value = readRegister(srcRegAddr);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovRegMem:
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{
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uint16_t addr = fetch16();
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uint8_t srcRegAddr = fetch8();
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int16_t value = readRegister(srcRegAddr);
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m_memory.write16(addr, value);
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}
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break;
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case data::OpCodes::MovMemReg:
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{
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uint8_t destRegAddr = fetch8();
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uint16_t addr = fetch16();
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int16_t value = m_memory.read16(addr);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovDerefRegReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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uint16_t addr = readRegister(srcRegAddr);
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int16_t value = m_memory.read16(addr);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovDerefRegMem:
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{
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uint16_t destAddr = fetch16();
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uint8_t srcRegAddr = fetch8();
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uint16_t addr = readRegister(srcRegAddr);
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int16_t value = m_memory.read16(addr);
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m_memory.write16(destAddr, value);
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}
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break;
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case data::OpCodes::MovImmRegOffReg:
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{
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uint8_t destRegAddr = fetch8();
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uint16_t addr = fetch16();
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uint8_t offRegAddr = fetch8();
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int16_t offset = readRegister(offRegAddr);
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int16_t value = m_memory.read16(addr + offset);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovRegDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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int16_t value = readRegister(srcRegAddr);
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write16(addr, value);
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}
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break;
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case data::OpCodes::MovMemDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint16_t srcAddr = fetch16();
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int16_t value = m_memory.read16(srcAddr);
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write16(addr, value);
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}
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break;
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case data::OpCodes::MovImmDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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int16_t value = fetch16();
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write16(addr, value);
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}
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break;
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case data::OpCodes::MovDerefRegDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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uint16_t srcAddr = readRegister(srcRegAddr);
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uint16_t destAddr = readRegister(destRegAddr);
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int16_t value = m_memory.read16(srcAddr);
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m_memory.write16(destAddr, value);
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}
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break;
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case data::OpCodes::MovByteImmMem:
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{
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uint16_t addr = fetch16();
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int8_t literal = fetch8();
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m_memory.write8(addr, literal);
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}
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break;
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case data::OpCodes::MovByteDerefRegMem:
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{
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uint16_t destAddr = fetch16();
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uint8_t srcRegAddr = fetch8();
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uint16_t addr = readRegister(srcRegAddr);
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int8_t value = m_memory.read8(addr);
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m_memory.write8(destAddr, value);
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}
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break;
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case data::OpCodes::MovByteRegDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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int16_t value = readRegister(srcRegAddr);
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write8(addr, (int8_t)value);
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}
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break;
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case data::OpCodes::MovByteMemDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint16_t srcAddr = fetch16();
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int8_t value = m_memory.read8(srcAddr);
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write8(addr, value);
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}
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break;
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case data::OpCodes::MovByteImmDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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int8_t value = fetch8();
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uint16_t addr = readRegister(destRegAddr);
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m_memory.write8(addr, value);
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}
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break;
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case data::OpCodes::MovByteDerefRegDerefReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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uint16_t srcAddr = readRegister(srcRegAddr);
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uint16_t destAddr = readRegister(destRegAddr);
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int8_t value = m_memory.read8(srcAddr);
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m_memory.write8(destAddr, value);
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}
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break;
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case data::OpCodes::MovByteMemReg:
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{
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uint8_t destRegAddr = fetch8();
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uint16_t srcAddr = fetch16();
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int8_t value = m_memory.read8(srcAddr);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovByteImmReg:
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{
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uint8_t destRegAddr = fetch8();
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int8_t value = fetch8();
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovByteDerefRegReg:
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{
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uint8_t destRegAddr = fetch8();
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uint8_t srcRegAddr = fetch8();
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uint16_t srcAddr = readRegister(srcRegAddr);
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int8_t value = m_memory.read8(srcAddr);
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writeRegister(destRegAddr, value);
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}
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break;
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case data::OpCodes::MovByteRegMem:
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{
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uint16_t addr = fetch16();
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uint8_t regAddr = fetch8();
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int16_t value = readRegister(regAddr);
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m_memory.write8(addr, (int8_t)(value & 0x00FF));
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}
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break;
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case data::OpCodes::AddImmReg:
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{
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uint8_t regAddr = fetch8();
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int16_t literal = fetch16();
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int16_t regValue = readRegister(regAddr);
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writeRegister(data::Registers::ACC, regValue + literal);
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}
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break;
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case data::OpCodes::AddRegReg:
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{
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uint8_t regAddr1 = fetch8();
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uint8_t regAddr2 = fetch8();
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int16_t regValue1 = readRegister(regAddr1);
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int16_t regValue2 = readRegister(regAddr2);
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writeRegister(data::Registers::ACC, regValue1 + regValue2);
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}
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break;
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case data::OpCodes::SubImmReg:
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{
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uint8_t regAddr = fetch8();
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int16_t literal = fetch16();
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int16_t regValue = readRegister(regAddr);
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writeRegister(data::Registers::ACC, regValue - literal);
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}
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break;
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case data::OpCodes::SubRegReg:
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{
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uint8_t regAddr1 = fetch8();
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uint8_t regAddr2 = fetch8();
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int16_t regValue1 = readRegister(regAddr1);
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int16_t regValue2 = readRegister(regAddr2);
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writeRegister(data::Registers::ACC, regValue1 - regValue2);
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}
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break;
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case data::OpCodes::MulImmReg:
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{
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uint8_t regAddr = fetch8();
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int16_t literal = fetch16();
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int16_t regValue = readRegister(regAddr);
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writeRegister(data::Registers::ACC, regValue * literal);
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}
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break;
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case data::OpCodes::MulRegReg:
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{
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uint8_t regAddr1 = fetch8();
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uint8_t regAddr2 = fetch8();
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int16_t regValue1 = readRegister(regAddr1);
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int16_t regValue2 = readRegister(regAddr2);
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writeRegister(data::Registers::ACC, regValue1 * regValue2);
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}
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break;
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case data::OpCodes::IncReg:
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{
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uint8_t regAddr = fetch8();
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int16_t regValue = readRegister(regAddr);
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writeRegister(regAddr, regValue + 1);
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}
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break;
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case data::OpCodes::DecReg:
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{
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uint8_t regAddr = fetch8();
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int16_t regValue = readRegister(regAddr);
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writeRegister(regAddr, regValue - 1);
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}
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break;
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case data::OpCodes::RShiftRegImm:
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{
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int16_t literal = fetch16();
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uint8_t regAddr = fetch8();
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int16_t regValue = readRegister(regAddr);
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regValue = regValue >> literal;
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writeRegister(regAddr, regValue);
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}
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break;
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case data::OpCodes::RShiftRegReg:
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{
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uint8_t shiftRegAddr = fetch8();
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uint8_t regAddr = fetch8();
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int16_t shiftValue = readRegister(shiftRegAddr);
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int16_t regValue = readRegister(regAddr);
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regValue = regValue >> shiftValue;
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writeRegister(regAddr, regValue);
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}
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break;
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case data::OpCodes::LShiftRegImm:
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{
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int16_t literal = fetch16();
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uint8_t regAddr = fetch8();
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int16_t regValue = readRegister(regAddr);
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regValue = regValue << literal;
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writeRegister(regAddr, regValue);
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}
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break;
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case data::OpCodes::LShiftRegReg:
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{
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uint8_t shiftRegAddr = fetch8();
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uint8_t regAddr = fetch8();
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int16_t shiftValue = readRegister(shiftRegAddr);
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int16_t regValue = readRegister(regAddr);
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regValue = regValue << shiftValue;
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writeRegister(regAddr, regValue);
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}
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break;
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case data::OpCodes::AndRegImm:
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{
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int16_t literal = fetch16();
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uint8_t regAddr = fetch8();
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int16_t value = readRegister(regAddr);
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writeRegister(data::Registers::ACC, value & literal);
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}
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break;
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case data::OpCodes::AndRegReg:
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{
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uint8_t andRegAddr = fetch8();
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uint8_t regAddr = fetch8();
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int16_t value = readRegister(regAddr);
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int16_t andValue = readRegister(andRegAddr);
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writeRegister(data::Registers::ACC, value & andValue);
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}
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break;
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case data::OpCodes::OrRegImm:
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{
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int16_t literal = fetch16();
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uint8_t regAddr = fetch8();
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int16_t value = readRegister(regAddr);
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writeRegister(data::Registers::ACC, value | literal);
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}
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break;
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case data::OpCodes::OrRegReg:
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{
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uint8_t andRegAddr = fetch8();
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uint8_t regAddr = fetch8();
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int16_t value = readRegister(regAddr);
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int16_t andValue = readRegister(andRegAddr);
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writeRegister(data::Registers::ACC, value | andValue);
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}
|
|
break;
|
|
case data::OpCodes::XorRegImm:
|
|
{
|
|
int16_t literal = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
writeRegister(data::Registers::ACC, value ^ literal);
|
|
}
|
|
break;
|
|
case data::OpCodes::XorRegReg:
|
|
{
|
|
uint8_t andRegAddr = fetch8();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t andValue = readRegister(andRegAddr);
|
|
writeRegister(data::Registers::ACC, value ^ andValue);
|
|
}
|
|
break;
|
|
case data::OpCodes::NotReg:
|
|
{
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
writeRegister(data::Registers::ACC, ~value);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpNotEqImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value != accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpNotEqReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value != accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpEqImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value == accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpEqReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value == accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpGrImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value > accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpGrReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value > accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpLessImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value < accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpLessReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value < accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpGeImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value >= accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpGeReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value >= accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpLeImm:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
int16_t value = fetch16();
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value <= accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::JmpLeReg:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
int16_t accValue = readRegister(data::Registers::ACC);
|
|
if (value <= accValue)
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::Jmp:
|
|
{
|
|
uint16_t addr = fetch16();
|
|
writeRegister(data::Registers::IP, addr);
|
|
}
|
|
break;
|
|
case data::OpCodes::Halt:
|
|
{
|
|
m_halt = true;
|
|
return false;
|
|
}
|
|
break;
|
|
case data::OpCodes::PushImm:
|
|
{
|
|
int16_t value = fetch16();
|
|
pushToStack(value);
|
|
}
|
|
break;
|
|
case data::OpCodes::PushReg:
|
|
{
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = readRegister(regAddr);
|
|
pushToStack(value);
|
|
}
|
|
break;
|
|
case data::OpCodes::PopReg:
|
|
{
|
|
uint8_t regAddr = fetch8();
|
|
int16_t value = popFromStack();
|
|
writeRegister(regAddr, value);
|
|
}
|
|
break;
|
|
case data::OpCodes::CallImm:
|
|
{
|
|
uint16_t subroutineAddr = fetch16();
|
|
pushStackFrame();
|
|
writeRegister(data::Registers::IP, subroutineAddr);
|
|
m_subroutineCounter++;
|
|
}
|
|
break;
|
|
case data::OpCodes::CallReg:
|
|
{
|
|
uint8_t regAddr = fetch8();
|
|
uint16_t subroutineAddr = readRegister(regAddr);
|
|
pushStackFrame();
|
|
writeRegister(data::Registers::IP, subroutineAddr);
|
|
m_subroutineCounter++;
|
|
}
|
|
break;
|
|
case data::OpCodes::Ret:
|
|
{
|
|
popStackFrame();
|
|
// m_subroutineCounter = ZERO(m_subroutineCounter - 1);
|
|
m_subroutineCounter--;
|
|
}
|
|
break;
|
|
case data::OpCodes::ArgReg:
|
|
{
|
|
uint8_t regAddr = fetch8();
|
|
if (!isInSubRoutine()) break;
|
|
int16_t pp_val = readRegister(data::Registers::PP);
|
|
int16_t arg_data = m_memory.read16(pp_val);
|
|
writeRegister(data::Registers::PP, pp_val - 2);
|
|
writeRegister(regAddr, arg_data);
|
|
}
|
|
break;
|
|
case data::OpCodes::RetInt:
|
|
{
|
|
m_isInInterruptHandler = false;
|
|
popStackFrame();
|
|
// m_subroutineCounter = ZERO(m_subroutineCounter - 1);
|
|
m_subroutineCounter--;
|
|
}
|
|
break;
|
|
case data::OpCodes::Int:
|
|
{
|
|
uint8_t intValue = fetch8();
|
|
if (!readFlag(data::Flags::InterruptsEnabled))
|
|
return true;
|
|
handleInterrupt(intValue);
|
|
m_subroutineCounter++;
|
|
}
|
|
break;
|
|
default:
|
|
{
|
|
data::ErrorHandler::pushError(data::ErrorCodes::CPU_UnknownInstruction, ostd::String("Unknown instruction: ").add(ostd::Utils::getHexStr(inst, true, 1)));
|
|
m_halt = true;
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void VirtualCPU::__debug_store_stack_frame_string_on_push(void)
|
|
{
|
|
if (!m_debugModeEnabled) return;
|
|
ostd::String stackFrameString = "";
|
|
|
|
uint16_t argStartAddr = readRegister(data::Registers::SP) + 2;
|
|
uint16_t argCount = m_memory.read16(argStartAddr);
|
|
if (argCount == 0)
|
|
argStartAddr = 0;
|
|
else
|
|
argStartAddr += (argCount * 2);
|
|
|
|
stackFrameString.add("args: ").add(ostd::Utils::getHexStr(argStartAddr, true, 2)).add(", argc: ").add(argCount).add("\n");
|
|
|
|
pushToStack(readRegister(data::Registers::R1));
|
|
stackFrameString.add("R1: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R1), true, 2));
|
|
pushToStack(readRegister(data::Registers::R2));
|
|
stackFrameString.add(" R2: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R2), true, 2));
|
|
pushToStack(readRegister(data::Registers::R3));
|
|
stackFrameString.add(" R3: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R3), true, 2));
|
|
pushToStack(readRegister(data::Registers::R4));
|
|
stackFrameString.add(" R4: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R4), true, 2));
|
|
pushToStack(readRegister(data::Registers::R5));
|
|
stackFrameString.add(" R5: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R5), true, 2));
|
|
pushToStack(readRegister(data::Registers::R6));
|
|
stackFrameString.add(" R6: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R6), true, 2));
|
|
pushToStack(readRegister(data::Registers::R7));
|
|
stackFrameString.add(" R7: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R7), true, 2));
|
|
pushToStack(readRegister(data::Registers::R8));
|
|
stackFrameString.add(" R8: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R8), true, 2));
|
|
pushToStack(readRegister(data::Registers::R9));
|
|
stackFrameString.add(" R9: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R9), true, 2));
|
|
pushToStack(readRegister(data::Registers::R10));
|
|
stackFrameString.add(" R10: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::R10), true, 2));
|
|
stackFrameString.add("\n");
|
|
pushToStack(readRegister(data::Registers::PP));
|
|
stackFrameString.add("PP: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::PP), true, 2));
|
|
pushToStack(readRegister(data::Registers::ACC));
|
|
stackFrameString.add(" ACC: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::ACC), true, 2));
|
|
pushToStack(readRegister(data::Registers::IP));
|
|
stackFrameString.add(" IP: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::IP), true, 2));
|
|
pushToStack(readRegister(data::Registers::FP));
|
|
stackFrameString.add(" FP: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::FP), true, 2));
|
|
stackFrameString.add("\n");
|
|
pushToStack(m_stackFrameSize);
|
|
stackFrameString.add("StackFrame: ").add(m_stackFrameSize).add(", ");
|
|
|
|
writeRegister(data::Registers::PP, argStartAddr);
|
|
writeRegister(data::Registers::FP, readRegister(data::Registers::SP));
|
|
stackFrameString.add("New FP: ").add(ostd::Utils::getHexStr(readRegister(data::Registers::FP), true, 2));
|
|
m_stackFrameSize = 0;
|
|
|
|
m_debug_stackFrameStrings.push_back(stackFrameString);
|
|
}
|
|
}
|
|
} |