204 lines
No EOL
9.2 KiB
C++
204 lines
No EOL
9.2 KiB
C++
#include "GlobalData.hpp"
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#include "../runtime/DragonRuntime.hpp"
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namespace dragon
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{
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namespace data
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{
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ostd::String OpCodes::getOpCodeString(uint8_t opCode)
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{
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CPUExtension* ext = DragonRuntime::cpu.getCurrentCPUExtension();
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if (ext != nullptr)
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return ext->getOpCodeString(DragonRuntime::cpu.getCurrentCPUExtensionInstruction());
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switch (opCode)
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{
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case data::OpCodes::NoOp: return "NoOp";
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case data::OpCodes::DEBUG_Break: return "debug_break";
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case data::OpCodes::BIOSModeImm: return "BIOSModeImm";
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case data::OpCodes::MovImmReg: return "MovImmReg";
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case data::OpCodes::MovImmMem: return "MovImmMem";
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case data::OpCodes::MovRegReg: return "MovRegReg";
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case data::OpCodes::MovRegMem: return "MovRegMem";
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case data::OpCodes::MovMemReg: return "MovMemReg";
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case data::OpCodes::MovDerefRegReg: return "MovDerefRegReg";
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case data::OpCodes::MovDerefRegMem: return "MovDerefRegMem";
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case data::OpCodes::MovImmRegOffReg: return "MovImmRegOffReg";
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case data::OpCodes::MovRegDerefReg: return "MovRegDerefReg";
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case data::OpCodes::MovMemDerefReg: return "MovMemDerefReg";
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case data::OpCodes::MovImmDerefReg: return "MovImmDerefReg";
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case data::OpCodes::MovDerefRegDerefReg: return "MovDerefRegDerefReg";
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case data::OpCodes::MovByteImmMem: return "MovByteImmMem";
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case data::OpCodes::MovByteRegMem: return "MovByteRegMem";
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case data::OpCodes::MovByteDerefRegMem: return "MovByteDerefRegMem";
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case data::OpCodes::MovByteImmDerefReg: return "MovByteImmDerefReg";
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case data::OpCodes::MovByteRegDerefReg: return "MovByteRegDerefReg";
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case data::OpCodes::MovByteMemDerefReg: return "MovByteMemDerefReg";
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case data::OpCodes::MovByteDerefRegDerefReg: return "MovByteDerefRegDerefReg";
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case data::OpCodes::MovByteMemReg: return "MovByteMemReg";
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case data::OpCodes::MovByteImmReg: return "MovByteImmReg";
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case data::OpCodes::MovByteDerefRegReg: return "MovByteDerefRegReg";
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case data::OpCodes::AddImmReg: return "AddImmReg";
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case data::OpCodes::AddRegReg: return "AddRegReg";
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case data::OpCodes::SubImmReg: return "SubImmReg";
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case data::OpCodes::SubRegReg: return "SubRegReg";
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case data::OpCodes::MulImmReg: return "MulImmReg";
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case data::OpCodes::MulRegReg: return "MulRegReg";
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case data::OpCodes::DivImmReg: return "DivImmReg";
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case data::OpCodes::DivRegReg: return "DivRegReg";
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case data::OpCodes::IncReg: return "IncReg";
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case data::OpCodes::DecReg: return "DecReg";
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case data::OpCodes::RShiftRegImm: return "RShiftRegImm";
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case data::OpCodes::RShiftRegReg: return "RShiftRegReg";
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case data::OpCodes::LShiftRegImm: return "LShiftRegImm";
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case data::OpCodes::LShiftRegReg: return "LShiftRegReg";
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case data::OpCodes::AndRegImm: return "AndRegImm";
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case data::OpCodes::AndRegReg: return "AndRegReg";
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case data::OpCodes::OrRegImm: return "OrRegImm";
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case data::OpCodes::OrRegReg: return "OrRegReg";
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case data::OpCodes::XorRegImm: return "XorRegImm";
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case data::OpCodes::XorRegReg: return "XorRegReg";
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case data::OpCodes::NotReg: return "NotReg";
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case data::OpCodes::NegReg: return "NegReg";
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case data::OpCodes::NegByteReg: return "NegByteReg";
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case data::OpCodes::JmpNotEqImm: return "JmpNotEqImm";
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case data::OpCodes::JmpNotEqReg: return "JmpNotEqReg";
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case data::OpCodes::JmpEqImm: return "JmpEqImm";
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case data::OpCodes::JmpEqReg: return "JmpEqReg";
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case data::OpCodes::JmpGrImm: return "JmpGrImm";
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case data::OpCodes::JmpGrReg: return "JmpGrReg";
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case data::OpCodes::JmpLessImm: return "JmpLessImm";
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case data::OpCodes::JmpLessReg: return "JmpLessReg";
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case data::OpCodes::JmpGeImm: return "JmpGeImm";
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case data::OpCodes::JmpGeReg: return "JmpGeReg";
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case data::OpCodes::JmpLeImm: return "JmpLeImm";
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case data::OpCodes::JmpLeReg: return "JmpLeReg";
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case data::OpCodes::Jmp: return "Jmp";
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case data::OpCodes::Halt: return "Halt";
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case data::OpCodes::PushImm: return "PushImm";
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case data::OpCodes::PushReg: return "PushReg";
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case data::OpCodes::PopReg: return "PopReg";
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case data::OpCodes::CallImm: return "CallImm";
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case data::OpCodes::CallReg: return "CallReg";
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case data::OpCodes::Ret: return "Ret";
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case data::OpCodes::ArgReg: return "ArgReg";
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case data::OpCodes::RetInt: return "RetInt";
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case data::OpCodes::Int: return "Int";
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case data::OpCodes::Ext01: return "Ext01";
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case data::OpCodes::Ext02: return "Ext02";
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case data::OpCodes::Ext03: return "Ext03";
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case data::OpCodes::Ext04: return "Ext04";
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case data::OpCodes::Ext05: return "Ext05";
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case data::OpCodes::Ext06: return "Ext06";
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case data::OpCodes::Ext07: return "Ext07";
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case data::OpCodes::Ext08: return "Ext08";
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case data::OpCodes::Ext09: return "Ext09";
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case data::OpCodes::Ext10: return "Ext10";
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case data::OpCodes::Ext11: return "Ext11";
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case data::OpCodes::Ext12: return "Ext12";
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case data::OpCodes::Ext13: return "Ext13";
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case data::OpCodes::Ext14: return "Ext14";
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case data::OpCodes::Ext15: return "Ext15";
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case data::OpCodes::Ext16: return "Ext16";
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default: return "UNKNOWN_INST";
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}
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}
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uint8_t OpCodes::getInstructionSIze(uint8_t opCode)
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{
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CPUExtension* ext = DragonRuntime::cpu.getCurrentCPUExtension();
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if (ext != nullptr)
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return ext->getInstructionSIze(DragonRuntime::cpu.getCurrentCPUExtensionInstruction());
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switch (opCode)
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{
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case data::OpCodes::NoOp: return 1;
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case data::OpCodes::DEBUG_Break: return 1;
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case data::OpCodes::BIOSModeImm: return 2;
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case data::OpCodes::MovImmReg: return 4;
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case data::OpCodes::MovImmMem: return 5;
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case data::OpCodes::MovRegReg: return 3;
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case data::OpCodes::MovRegMem: return 4;
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case data::OpCodes::MovMemReg: return 4;
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case data::OpCodes::MovDerefRegReg: return 3;
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case data::OpCodes::MovDerefRegMem: return 4;
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case data::OpCodes::MovImmRegOffReg: return 5;
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case data::OpCodes::MovRegDerefReg: return 3;
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case data::OpCodes::MovMemDerefReg: return 4;
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case data::OpCodes::MovImmDerefReg: return 4;
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case data::OpCodes::MovDerefRegDerefReg: return 3;
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case data::OpCodes::MovByteImmMem: return 4;
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case data::OpCodes::MovByteRegMem: return 4;
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case data::OpCodes::MovByteDerefRegMem: return 4;
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case data::OpCodes::MovByteImmDerefReg: return 3;
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case data::OpCodes::MovByteRegDerefReg: return 3;
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case data::OpCodes::MovByteMemDerefReg: return 4;
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case data::OpCodes::MovByteDerefRegDerefReg: return 3;
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case data::OpCodes::MovByteMemReg: return 4;
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case data::OpCodes::MovByteImmReg: return 3;
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case data::OpCodes::MovByteDerefRegReg: return 3;
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case data::OpCodes::AddImmReg: return 4;
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case data::OpCodes::AddRegReg: return 3;
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case data::OpCodes::SubImmReg: return 4;
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case data::OpCodes::SubRegReg: return 3;
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case data::OpCodes::MulImmReg: return 4;
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case data::OpCodes::MulRegReg: return 3;
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case data::OpCodes::DivImmReg: return 4;
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case data::OpCodes::DivRegReg: return 3;
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case data::OpCodes::IncReg: return 2;
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case data::OpCodes::DecReg: return 2;
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case data::OpCodes::RShiftRegImm: return 4;
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case data::OpCodes::RShiftRegReg: return 3;
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case data::OpCodes::LShiftRegImm: return 4;
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case data::OpCodes::LShiftRegReg: return 3;
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case data::OpCodes::AndRegImm: return 4;
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case data::OpCodes::AndRegReg: return 3;
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case data::OpCodes::OrRegImm: return 4;
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case data::OpCodes::OrRegReg: return 3;
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case data::OpCodes::XorRegImm: return 4;
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case data::OpCodes::XorRegReg: return 3;
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case data::OpCodes::NotReg: return 2;
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case data::OpCodes::NegReg: return 2;
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case data::OpCodes::NegByteReg: return 2;
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case data::OpCodes::JmpNotEqImm: return 5;
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case data::OpCodes::JmpNotEqReg: return 4;
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case data::OpCodes::JmpEqImm: return 5;
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case data::OpCodes::JmpEqReg: return 4;
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case data::OpCodes::JmpGrImm: return 5;
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case data::OpCodes::JmpGrReg: return 4;
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case data::OpCodes::JmpLessImm: return 5;
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case data::OpCodes::JmpLessReg: return 4;
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case data::OpCodes::JmpGeImm: return 5;
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case data::OpCodes::JmpGeReg: return 4;
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case data::OpCodes::JmpLeImm: return 5;
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case data::OpCodes::JmpLeReg: return 4;
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case data::OpCodes::Jmp: return 3;
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case data::OpCodes::Halt: return 1;
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case data::OpCodes::PushImm: return 3;
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case data::OpCodes::PushReg: return 2;
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case data::OpCodes::PopReg: return 2;
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case data::OpCodes::CallImm: return 3;
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case data::OpCodes::CallReg: return 2;
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case data::OpCodes::Ret: return 1;
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case data::OpCodes::ArgReg: return 2;
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case data::OpCodes::RetInt: return 1;
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case data::OpCodes::Int: return 2;
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case data::OpCodes::Ext01: return 0;
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case data::OpCodes::Ext02: return 0;
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case data::OpCodes::Ext03: return 0;
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case data::OpCodes::Ext04: return 0;
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case data::OpCodes::Ext05: return 0;
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case data::OpCodes::Ext06: return 0;
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case data::OpCodes::Ext07: return 0;
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case data::OpCodes::Ext08: return 0;
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case data::OpCodes::Ext09: return 0;
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case data::OpCodes::Ext10: return 0;
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case data::OpCodes::Ext11: return 0;
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case data::OpCodes::Ext12: return 0;
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case data::OpCodes::Ext13: return 0;
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case data::OpCodes::Ext14: return 0;
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case data::OpCodes::Ext15: return 0;
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case data::OpCodes::Ext16: return 0;
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default: return 0;
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}
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}
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}
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} |